SARA R4/N4 series

Transcript

1 R4/N4 series SARA - System Integration Manual System Integration Manual - SARA R4/N4 Abstract This document - R4/N4 series describes the features and the integration of the size - optimized SARA cellular modules. These modules are a complete, cost efficient, performance optimized, multi - mode m factor. and multi band LTE Cat M1 / NB1 and EGPRS solution in the compact SARA for www.u - blox.com - R11 16029218 - UBX

2 - - System Integration Manual SARA R4/N4 series Document Information Title SARA - R4/N4 series System Integration Manual Subtitle System Integration Manual Document type - 16029218 Document number UBX R1 1 20 - Feb - 201 9 Revision and date Disclosure Restriction Product status status Corresponding content Draft For functional testing. Revised and supplementary data will be published later. Functional Sample In Development / Objective Specification T arget values. Revised and supplementary data will be published later. Prototype Engineering Sample Data based on early testing. Revised and supplementary data will be published later. Advance Information Data from product verification. Revised and supplementary data may be published later. Initial Production Early Production Information Mass Production / Production Information Document contains the final product specification. End of Life This document applies to the following products: Product name Type number Modem version Application version PCN reference Product status 00 SARA R404M SARA - R404M - 00B - - K0.0.00.00.07.06 UBX - 17047084 End of Life R404M - SARA Initial Production 18053670 - UBX K0.0.00.00.07.08 01 - 00B - SARA - R410M - 01B - 00 R410M L0.0.00.00.02.03 UBX - 17051617 Initial Production - SARA SARA - R410M - 02B - 00 L0.0.00.00.05.06 A02.00 UBX - 18010263 Initial Production 18045915 SARA - R410M - 52B - 00 L0.0.00.00.06.05 A02.06 UBX - Initial Production M0.09.00 Initial Production 19004091 - UBX 00 A02.11 SARA - R412M - SARA - R412M - 02B Initial Production 18057459 - UBX SARA - N410 SARA - N410 - 02B - 00 A02.09 L0.0.00.00.07.07 blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this u - document or any part thereof is only document. Copying, reproduction, modification or disclosure to third parties of this . blox permitted with the express written permission of u - its use blox assumes no liability for - The information contained herein is provided “as is” and u . No warranty, either express or not limited implied, is given, including but , with respect to the accuracy, correctness, reliability and fitness for a particular to the purpose of the information. This document may be revised by u - blox at any time most recent without notice . For documents, visit www.u - blox.com. blox AG. - ht © u Copyrig 16029218 - R11 - UBX Page 2 of 116

3 - - System Integration Manual SARA R4/N4 series ontents C ... ... ... 2 Document Information ... ... ... ... ... ... Contents 3 ... ... ... System description 6 1 ... Overview ... ... ... ... ... 6 1.1 ... 1.2 ... ... ... ... 9 Architecture ... out ... ... ... - ... 10 1.3 Pin Operating modes ... ... 1.4 ... ... 14 ... 1.5 Supply interfa ces ... ... ... ... 17 ... ... 1.5.1 17 ... ... Module supply input (VCC) ... 1.5.2 Generic digital interfaces supply output (V_INT) ... ... ... 22 1.6 System function interfaces ... ... ... ... 23 ... 1.6.1 Module power - on ... ... ... 23 24 1.6. 2 Module power - off ... ... ... ... ... 1.6.3 ... ... ... Module reset ... 26 1.7 Antenna interface ... ... ... ... ... 27 27 1.7.1 Antenna RF interface (ANT) ... ... ... ... 1.7.2 Antenna detection interface (ANT_DET) ... ... ... 28 ... ... 28 ... 1.8 SIM interface ... ... SIM interface 1.8.1 28 ... ... ... ... ... 1.8.2 ... ... ... ... 28 SIM detection interface ... Data communication interfaces ... ... ... 29 1.9 UART interface ... ... ... ... .. 29 1.9.1 ... ... ... ... USB interface ... 31 1.9.2 ... SPI interface ... ... 1.9.3 ... ... 32 ... 1.9.4 ce ... ... ... SDIO interfa ... 32 2 DDC (I ... C) interface 1.9.5 ... ... ... 32 ... 1.10 Audio ... ... ... ... 32 1.11 General Purpose Input/Output ... ... ... ... 33 33 ... 1.12 Reserved pins (RSVD) ... ... ... 1.13 ... ... ... ... ... 34 System features ... ... ... Network indication ... 34 1.13.1 1.13.2 Antenna supervisor ... ... ... ... 34 ... 1.13.3 Dual stack IPv4/IPv6 ... ... ... 34 ... 1.13.4 TCP/IP and UDP/IP ... ... ... 34 ... 1.13.5 ... ... ... FTP ... 34 1.13.6 HTTP ... ... ... ... ... 35 1.13.7 Firmware update Over AT (FOAT) ... ... ... . 35 1.13.8 Firmware update Over The Air (uFOTA) ... ... ... 35 35 ... 1.13.9 Power saving ... ... ... ... in - Design 2 38 ... ... ... ... ... 16029218 - R11 - UBX Page 3 of 116

4 R4/N4 series - System Integration Manual SARA - ... ... ... ... ... 38 2.1 Overview Supply interfaces ... ... 2.2 ... ... 39 ... 2.2.1 Module supply (VCC) ... ... ... 39 ... 2.2.2 Generic digital interfaces supply output (V_INT) ... ... ... 55 ... 2.3 ... ... System functions interfaces ... 56 2.3.1 Module power - on (PWR_ON) ... ... ... ... 56 ... 2.3.2 ... ... Module reset (RESET_N) ... 57 Antenna interface ... ... ... ... ... 58 2.4 ... ... ... ... Antenna RF interface (ANT) 58 2.4.1 2.4.2 ... ... ... 65 Antenna detection interface (ANT_DET) ... ... ... ... 2.5 ... 68 SIM interface 2.5.1 Guidelines for SIM circuit design ... ... ... ... 68 ... 2.5.2 ... ... Guidelines for SIM layout design ... 72 2.6 Data communication interfaces ... ... ... ... 73 2.6. UART interface 1 ... ... ... ... .. 73 2.6.2 ... ... ... ... ... 78 USB interface ... 2.6.3 ... ... ... SPI interface ... 80 2.6.4 SDIO interface ... ... ... ... .. 80 2 ... DDC (I 2.6.5 C) interface ... ... ... 80 82 ... ... ... ... ... 2.7 Audio 82 ... ... ... Guidelines for Audio circuit design 2.7.1 2.8 ... ... ... ... 83 General Purpose Input/Output . ... ... ... 83 2.8.1 Guidelines for GPIO circuit design Guidelines for general purpose input/output layout design ... ... 83 2.8.2 ... ... ... ... Reserved pins (RSVD) 84 2.9 Module placement ... ... ... ... ... 2.10 84 ... 2.11 ... ... Module footprint and paste mask ... 85 2. 12 Thermal guidelines ... ... ... ... ... 86 ... 2.13 Schematic for SARA - R4/N4 series module integration ... ... 87 2.13.1 Schematic for SARA - R4/N4 series modules ... ... ... 87 ... ... ... ... 88 ... 2.14 Design - in checklist 2.14.1 ... ... ... ... 88 Schematic checklist ... 2.14.2 ... ... Layout checklist ... 88 2.14.3 Antenna checklist ... ... ... ... 89 3 Handling and soldering ... ... ... ... 90 3.1 Packaging, shipping, storage and moisture preconditioning ... ... 90 3.2 Handling ... ... ... ... ... 90 ... 3.3 ... ... ... Soldering ... 91 3.3.1 Soldering paste ... ... ... ... . 91 ... 3.3.2 ... ... Reflow soldering ... 91 Optical in spection ... ... ... ... 92 3.3.3 ... ... ... ... ... 92 3.3.4 Cleaning 3.3.5 93 ... ... ... ... Repeated reflow soldering UBX 1602921 8 - R11 - Page 4 of 116

5 R4/N4 series - System Integration Manual SARA - .. ... ... ... ... 3.3.6 93 Wave soldering ... 3.3.7 ... ... ... Hand soldering .. 93 3.3.8 Rework ... ... ... ... ... 93 ... 3.3.9 ... ... Conformal coating ... 93 Casting ... ... ... ... ... 93 3.3.10 ... ... ... ... 94 3.3.11 Grounding metal covers ... 3.3.12 ... ... Use of ultrasonic processes ... 94 4 Approvals ... ... ... ... ... 95 ... 4.1 Product certification approval overview ... ... 95 ... 4.2 US Federal Communications Commission notice ... ... 97 4.2.1 Safety warnings review the structure ... ... ... 97 4.2.2 Declaration of Conformity ... ... ... ... 97 ... 4.2.3 Modifications ... ... ... ... 98 Innovation, Science, Economic Development Canada notice ... ... 98 4.3 ... ... ... ... Declaration of Conformity 4.3.1 98 ... 4.3.2 ... ... ... ... 99 Modifications European Conformance CE mark ... ... ... ... 101 4.4 Taiwanese National Communication Commission ... ... ... 4.5 101 5 Product testing ... ... ... ... .. 102 production test 5.1 u - blox in - series ... ... ... ... 102 5.2 Test parameters for OEM manufacturers ... ... ... 103 ... ... ... “Go/No go” tests for integrated devices 103 5.2.1 ... 5.2.2 ... ... RF functional tests ... 103 Appendix ... ... ... ... ... 105 ... A Migration between SARA modules ... ... 105 ... A.1 Overview ... ... ... ... 105 ... A.2 - out comparison ... Pin ... ... 107 B Glossary ... ... ... ... ... 112 Related documents ... ... ... ... .. 114 ... ... ... 115 ... ... Revision history Contact 116 ... ... ... ... ... 16029218 - R11 - UBX Page 5 of 116

6 SARA - - System Integration Manual R4/N4 series System description 1 Overview 1.1 R4/N4 - comprises LTE Cat M1, LTE Cat NB1 and EGPRS multi - mode modules in the SARA series The x 16.0 mm, 96 - pin), that allow easy integration in compact - SARA LGA form miniature factor (26.0 - in migration from u - blox cellular module families . designs and a seamless drop R4/N4 series modules are form - factor compatible w - blox LISA, LARA and TOBY cellular - SARA ith u to - pin compatible with u - blox SARA - N, SARA module families and are pin G and SARA - U cellular - - - - IoT, GSM/GPRS, CDMA, UMTS/HSPA and module families. This facilitates migration from u blox NB other LTE modules, maximizes customer investments, simplifies logistics, and enables very short market. See Table 1 to for a summary of the main features and interfaces. time - - The modules are ideal for LPWA applications with low to medium data throughput rates, as well as , such as connected health, smart metering, smart cities devices that require long battery lifetimes and wearables. support handover capability and delivers the technology necessary for use in The modules requisite. Oth applications such as vehicle, asset and people tracking where mobility is a pre er - applications where the modules are well - suited include and are not limited to: smart home, security systems, industrial monitoring and control. – 40 to The modules support data communication over an extended operating temperature range of tremely low power consumption, and with coverage enhancement for deeper range into +85 °C, with ex buildings and basements (and underground with NB1). Region Bands Positioning Interfaces Model Audio Features Grade (FOTA) band ® - C) 2 AssistNow software USB 2.0 Digital audio DDC (I Power Saving Mode GNSS via modem eDRX UART Antenna supervisor SPI Embedded TCP/UDP stack Standard Embedded HTTP, FTP (E)GPRS 4 Dual stack IPv4/IPv6 LTE FDD bands FW update over the air 3GPP LTE category 3GPP Release Baseline GPIOs Professional SDIO Automotive Analog audio CellLocate - USA 13 M1 13 ● ● ● SARA ● ● ● ● ● ● ● R404M North 2,4 ● ● ● ● ● ● SARA - R410M - 01B ● 13 M1 ● ● ● America 5,12 M1 - R410M - 02B Multi Region 13 ○ * ● ● ○ ● ● SARA ○ ● ● ○ ● ● ● ● ● ● ● ● NB1 North 2,4,5 ● ● ● ● ● ● ● SARA - R410M - 52B ● ● 13 M1 ● ● ● ○ ● ● ○ ○ America 12,13 M1 ● ● ● ● ● ● ● ● SARA - R412M - 02B Multi Region 13 ● * ● ● ● ○ ● ● ○ ○ ● NB1 ● ● ● ● ● ● ● ● SARA - N410 - 02B Multi Region 13 NB1 * ● ● ○ ● ● ○ ○ ● ● * = LTE Cat M1/NB1 Bands may include 1, 2, 3, 4, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28 (and band 39 in M1 - only) ○ ● = supported by future FW versions = supported by all FW versions R4/N4 series - SARA : 1 Table main features summary - 16029218 116 of 6 Page - System description R11 UBX

7 SARA R4/N4 series - System Integration Manual - - R4/N4 series modules include the following variants / product versions: SARA SARA R404M LTE Cat M1 module,  - mainly designed for operation in LTE band 13 SARA - R410M - 01B LTE Cat M1 module,  mainly designed for operation in LTE bands 2, 4, 5, 12 SARA - R410M - 02B LTE Cat M1 / NB1 module,  mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20, 28 52B LTE Cat M1 module, -  - SARA R410M mainly designed for operation in LTE bands 2, 4, 5, 12, 13  SARA - R412M - 02B LTE Cat M1 / NB1 and 2G module, mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 20 and 2G Quad band - - N410 - 02B LTE Cat NB1 module,  SARA mainly designed for operation in LTE bands 2, 3, 4, 5, 8, 12, 13, 28 Table summarizes 2 es characteristi cs and features of the modules. cellular radio access technologi Item SARA - R404M SARA - R410M SARA - R412M SARA - N410 Protocol stack 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13 Duplex - Half LTE Cat M1 Duplex - Duplex - Half LTE Cat NB1 Duplex - Half LTE Cat M1 RAT LTE Cat M1 Half 1 Duplex LTE Cat NB1 Half - LTE Cat NB1 - Half Duplex 2G GPRS / EGPRS Band 12 (700 MHz) LTE FDD bands Band 12 (700 MHz) Band 13 (750 MHz) Band 12 (700 MHz) 1 , 2 , 3 Band 17 (700 MHz) Band 28 (700 MHz) Band 13 (750 MHz) 1 Band 13 (750 MHz) Band 28 (700 MHz) Band 20 (800 MHz) 1 Band 20 (800 MHz) Band 13 (750 MHz) Band 5 (850 MHz) 1 Band 5 (850 MHz) Band 20 (800 MHz) Band 8 (900 MHz) 1 2 , Band 26 (850 MHz) Band 8 (900 MHz) Band 4 (1700 MHz) 1 , 2 Band 4 (1700 MHz) Band 3 (1800 MHz) Band 18 (850 MHz) Band 3 (1800 MHz) Band 2 (1900 MHz) Band 5 (850 MHz) , 1 2 Band 19 (850 MHz) Band 2 (1900 MHz) 1 Band 8 (900 MHz) Band 4 (1700 MHz) 1 Band 3 (1800 MHz) Band 2 (1900 MHz) 1 3 , 2 , Band 25 (1900 MHz) 1 Band 1 (2100 MHz) 3 , 4 LTE TDD bands Band 39 (1900 MHz) bands GSM 850 MHz 2G E - GSM 900 MHz DCS 1800 MHz PCS 1900 MHz 1 the “01” product version. Not supported by 2 the “52” product version. Not supported by 3 Not supported in signaling mode by the “02” product version 4 NB category product versions. the “01” and “52” Not supported by . 1 upported in LTE s Not System description 16029218 - R11 - UBX Page 7 of 116

8 SARA - System Integration Manual - R4/N4 series - Item SARA N410 R404M SARA - R410M SARA - R412M SARA - 5 Power class LTE category M1 / NB1: : LTE category NB1: LTE Cat M1 / NB1 LTE Cat M1: Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) 2G GMSK: Class 4 (33 dBm) for - GSM bands GSM/E Class 1 (30 dBm) for DCS/PCS bands - PSK: 2G 8 Class E2 (27 dBm) for GSM/E - GSM bands Class E2 (26 dBm) for DCS/PCS bands LTE category M1: LTE category M1: Data rate LTE category NB1: LTE category M1: up to 375 kb/s UL up to 375 kb/s UL up to 62.5 kb/s UL up to 375 kb/s UL up to 27.2 kb/s DL up to 300 kb/s DL up to 300 kb/s DL up to 300 kb/s DL 5 : LTE category NB1 LTE category NB1: up to 62.5 kb/s UL up to 62.5 kb/s UL up to 27.2 kb/s DL up to 27.2 kb/s DL 6 GPRS multi - slot class 33 : Up to 85.6 kb/ s UL Up to 107 kb/s DL 6 slot class 33 : EGPRS multi - Up to 236.8 kb/s UL Up to 296.0 kb/s DL GPRS LTE Cat M1, LTE Cat NB1, EGPRS and R4/N4 series Table 2 : SARA - characteristics summary modules 5 Not supported by the “01” product version. 6 with 6 slots in total. ink L own slot class 33 implies a maximum of 5 slots in D - GPRS/EGPRS multi - Link - p and 4 slots in U UBX 16029218 - R11 System description - Page 8 of 116

9 - SARA - System Integration Manual R4/N4 series 1.2 Architecture R4/N4 series - SARA summarizes the internal architecture of 1 Figure . modules PA Filter SIM ANT Switch SIM card detection RF transceiver UART USB Cellular 2 DDC (I C) BaseBand Processor SDIO Memory 19.2 MHz SPI / Digital Audio VCC (Supply) GPIOs V_INT Antenna detection Power Reset Management Power - On modules simplified block diagram R4/N4 series - SARA : 1 Figure 01B modules, i.e. the “00” and “01” product versions of the - R410M - ☞ 00B and SARA SARA - R404M - R4/N4 series - , do not support the following interfaces, which should be left modules SARA unconnected and should not be driven by external devices: 2 DDC (I C) interface o o SDIO interface SPI interface o o Digital audio interface ☞ - R412M - 02B and SARA 02B modules, i.e. the - N410 - 52B, SARA SARA - R410M - 02B, SARA - R410M - SARA , do not support the following R4/N4 series “02” and “52” product versions - modules of the interfaces, which should be left unconnected and should not be driven by external devices: SDIO interface o o SPI interface Digital audio interface o System description 16029218 - R11 - UBX Page 9 of 116

10 SARA System Integration Manual - R4/N4 series - out 1.3 Pin - - Table 3 lists the pin out of the SARA - R4/N4 series modules, with pins grouped by function. Pin No Pin Name Function Remarks Description I/O Module supply VCC supply circuit affects the RF performance and VCC 51, 52, 53 Power I input compliance of the device integrating the module with applicable required certification schemes. 1.5.1 See section for functional description / requirements. for external circuit design - in. See section 2.2.1 1, 3, 5, 14, N/A GND Ground GND pins are internally connected each other. 22, 30, - 20 External ground connection affects the RF and thermal 32, 43, performance of the device. 50, 54, for functional description. 1.5.1 See section 61, 55, 57 - - 2.2.1 in. for external circuit design See section - 96 63 Generic digital V_INT = 1.8 V (typical) generated by internal regulator when 4 O V_INT interfaces supply the module is switched on, outside the low power PSM deep output sleep mode. Test - Point for diagnostic access is recommended. for functional description. See section 1.5.2 - for external circuit design 2.2.2 See section in. - on input System PWR_ON 15 I Power  up resistor. - Internal 200 k pull Test Point for diagnostic access is recommended. - 1.6.1 See section for functional desc ription. See section in. - for external circuit design 2.3.1 External reset 18 I RESET_N up resistor. - pull  Internal 37 k input Test diagnostic access is recommended. Point for - See section 1.6.3 for functional description. 2.3.2 - in. See section for external circuit design ANT 56 I/O Antenna Primary antenna Main Tx / Rx antenna interface. 50  nominal characteristic impedance. Antenna circuit affects the RF performance and application device compliance with required certification schemes. See section 1.7 for functional description / requirements. See section 2.4 for external circuit design - in. 62 I Antenna detection ADC for antenna presence detection function ANT_DET See section 1.7.2 for functional description. See section 2.4.2 for external circuit design - in. SIM supply output VSIM = 1.8 V / 3 V output as per the connected SIM type. SIM VSIM 41 O See section 1.8 for functional description. .5 2 See section - in. for external circuit design SIM data 39 I/O Data input/output for 1.8 V / 3 V SIM SIM_IO Internal 4.7 k  pull - up to VSIM. See section 1.8 for functional description. in. See sect ion 2.5 for external circuit design - SIM clock O 38 SIM_CLK 4.8 MHz clock output for 1.8 V / 3 V SIM See section 1.8 for functional description. 2.5 in. for external circuit design - See section SIM_RST Reset output for 1.8 V / 3 V SIM SIM reset 40 O 1.8 See section for functional description. in. - for external circuit design 2.5 e section Se T V.24, - 1.8 V output, Circuit 104 (RXD) in ITU UART UART data output O 13 RXD for AT commands, data communication, FOAT. See section 1.9.1 for functional description. 2.6.1 See section in. - for external circuit design System description 16029218 - R11 - UBX Page 10 of 116

11 SARA System Integrat ion Manual - R4/N4 series - Function Remarks Pin Name Pin No I/O Description - 1.8 V input, Circuit 103 (TXD) in ITU T V.24, I TXD UART data input 12 for AT commands, data communication, FOAT. down to GND on “00” and R410M 02 Internal pull - versions - B - up to V_INT on other product versions Internal pull See section for functional description. 1.9.1 2.6.1 in. - for external circuit design See section UART clear to CTS T V.24. - 1.8 V output, Circuit 106 (CTS) in ITU O 11 send output Not supported by ‘00’, ‘01’ and R410M 02B versions - . See section for functional description. 1.9.1 2.6.1 See section in. - for external circuit design UART ready to RTS I T V.24. - 1.8 V input, Circuit 105 (RTS) in ITU 10 send input - up to V_INT. Internal active pull . Not supported by ‘00’, ‘01’ and R410M - 02B versions 1.9.1 See section for functional description. 2.6.1 See section for external circuit design - in. UART data set 6 1.8 V, Circuit 107 in ITU O - T V.24. DSR ready output for functional description. 1.9.1 See section - See section 2.6.1 for external circuit design in. UART ring RI O 7 1.8 V, Circuit 125 in ITU - T V .24. indicator output 1.9.1 for functional description. See section 2.6.1 for external circuit design - in. See section UART data 9 I DTR 1.8 V, Circuit 108/2 in ITU - T V.24. terminal ready up to V_INT. Internal active pull - input See section 1.9.1 for functional description. See section 2.6.1 for external circuit design - in. UART data carrier 1.8 V, Circuit 109 in ITU D CD 8 O T V.24. - detect output 1.9.1 for functional description. See section 2.6.1 for external circuit design - in. See section VBUS (5 V typical) USB supply generated by the host must VUSB_DET 17 I USB detect input USB be connected to this input pin to enable the USB interface. Test - Point for diagnostic / FW update strongly recommended. See section 1.9.2 for functional descriptio n. - See section 2.6.2 for external circuit design in. USB interface for AT commands, data communication, USB Data Line D I/O 28 - USB_D - FOAT, FW update by u - blox tool , diagnostics. nominal differential impedance (Z 90  ) 0 30  nominal common mode impedance (Z ) CM down resistors and external series resistors - up or pull Pull - as required by the USB 2.0 specifications [4] are part of the USB pin driver and need n ot be provided externally. Point for diagnostic / FW update strongly - Test recommended. See section 1.9.2 for functional description. See section in. 2.6.2 for external circuit design - USB interface for AT commands, data communication, 29 USB_D+ USB Data Line D+ I/O , FOAT, FW update by u - blox tool diagnostics. ) 90  nominal differential impedance (Z 0 ) 30  nominal common mode impedance (Z CM - up or pull - down resistors and external series resistors Pull as required by the USB 2.0 specifications [4] are part of the USB pin driver and need not be provided externally. Test - Point for diagnostic / FW update strongly recommended. for functional description. See section 1.9.2 - for external circuit design 2.6.2 See section in. System description 16029218 - R11 - UBX Page 11 of 116

12 SARA System Integration Manual - R4/N4 series - Pin No I/O Description Remarks Function Pin Name I2S_WA / SPI Master Output Slave Input, alternatively configurable as SPI O SPI MOSI 34 2 I S word alignment SPI_MOSI Not supported by “00”, “01” and “ x2 ” product versions. See section 1.9.3 for functional description. See section for external circuit design - in. 2.6.3 I2S_RXD / SPI Master Input Slave Output, alternatively configurable as I SPI MISO 37 2 SPI_MISO I S receive data Not supported by “00”, “01” and “ ” product versions. x2 See section 1.9.3 for functional description. See section 2.6.3 for external circuit design - in. 2 I2S_CLK / SPI clock S clock I SPI clock, alternatively configurable as O 36 SPI_CLK Not supported by “00”, “01” and “ x2 ” product versions. See section 1.9.3 for functional description. in. - for external circuit design See section 2.6.3 2 I2S_TXD / S transmit data I 35 O as SPI Chip Select SPI Chip Selec t, alternatively settable SPI_CS x2 ” product versions. Not supported by “00”, “01” and “ for functional description. 1.9.3 See section See section 2.6.3 for external circuit design - in. SDIO serial data ” product versions. Not supported by “00”, “01” and “ SDIO SDIO_D0 47 I/O x2 [0] See section 1.9.4 for functional description. in. - for external circuit design See section 2.6.4 Not supported by “00”, “01” and “ ” product versions. x2 SDIO_D1 49 I/O SDIO serial data [1] See section for functional description. 1.9.4 See section 2.6.4 for external circuit design - in. SDIO serial data Not supported by “00”, “01” and “ I/O 44 SDIO_D2 ” product versions. x2 [2] 1.9.4 for functional description. See section 2.6.4 for external circuit design - in. See section SDIO serial data S DIO_D3 48 I/O ” product versions. Not supported by “00”, “01” and “ x2 [3] See section 1.9.4 for functional description. See sectio n 2.6.4 for external circuit design - in. SDIO_CLK O 45 SDIO serial clock Not supported by “00”, “01” and “ x2 ” product versions. See section for functional description. 1.9.4 2.6.4 for external circuit design - in. See section 46 SDIO_CMD I/O SDIO command Not supported by “00”, “01” and “ x2 ” product versions. See section 1.9.4 for functional description. See section 2.6.4 for external circuit design - in. 2 1.8 V open drain, for communication with I2C C bus clock line slave devices. - DDC SCL 27 O I Internal pull - up is not required. - up to V_INT: external pull Not supported by “00” and “01” product versions. 1.9.5 for functional description. See section 2.6.5 See section for external circuit design - in. 2 SDA I/O 26 I C bus data line 1.8 V open drain, for communication with I2C - slave devices. Internal pull - up to V_INT: external pull - up is not required. Not supported by “00” and “01” product versions. for functional description. See section 1.9.5 See section for external circuit design in. - 2.6.5 2 2 SPI Chip I2S_TXD / S transmit data, alternatively configurable as I O I Audio 35 S transmit data SPI_CS Select Not supported by “00”, “01” and “ x2 ” product versions. for functional description. 1.10 See section 2.7 in. See section - for external circuit design 2 2 I2S_RXD / I SPI Master S receive data, alternatively configurable as 37 receive data S I I Input Slave Output SPI_MISO ” product versions. Not supported by “00”, “01” and “ x2 1.10 See section for functional description. See section in. - for external circuit design 2.7 System description 16029218 - R11 - UBX Page 12 of 116

13 SARA - System Integration Manual - R4/N4 series Remarks Description I/O Function Pin Name Pin No 2 2 I2S_CLK / 36 alternatively configurable as I/O SPI clock I I S clock S clock, SPI_CLK Not supported by “00”, “01” and “ ” product versions. x2 for functional description. 1.10 See section in. - for external circuit design 2.7 tion See sec 2 2 I S word alignment, alternatively configurable as I2S_WA / 34 S word alignment I/O I SPI_MOSI Master Output Slave Input SPI Not supported by “00”, “01” and “ x2 ” product versions. 1.10 for functional description. See section See section 2.7 for external circuit design - in. 16 PIO1 GPIO 1.8 V GPIO with alternatively configurable functions. I/O GPIO G for functional description. 1.11 See section - for external circuit design in. 2.8 See section GPIO I/O 1.8 V GPIO with alternatively configurable functions. 23 GPIO2 for functional description. 1.11 See section See section 2.8 for external circuit design - in. 1.8 V GPIO with alternatively configurable functions. GPIO3 24 I/O GPIO for functional description. 1.11 See section - See section 2.8 for external circuit design in. 1.8 V GPIO with alternatively configurable functions. GPIO I/O GPIO4 25 for functional description. 1.11 See section in. - 2.8 See section for external circuit design I/O GPIO5 42 GPIO 1.8 V GPIO with alternatively configurable functions. 1.11 See section for functional description. See section 2.8 for external circuit design - in. GPIO6 GPIO 1.8 V GPIO with alternatively configurable functions. I/O 19 for functional description. 1.11 See section - See section 2.8 for external circuit design in. 33 RSVD This pin can be connected to GND. Reserved pin N/A Reserved 1.12 See sections and 2.9 Leave unconnected. Reserved pin N/A RSVD 2, 31 and 2.9 1.12 See sections grouped by function pin definition, s module - SARA : 3 Table R4/N4 series System description 16029218 - R11 - UBX Page 13 of 116

14 R4/N4 series SARA System Integration Manual - - 1.4 Operating modes SARA Table e defined in modules have several operating modes. The operating modes ar - R4/N4 series Table 4 and described in detail in 5 , providing general guidelines for operation. Operating Mode Definition General Status supply not present or below operating range: module is switched off. VCC Powered Mode - Not down - Power Off Mode Power - VCC supply within operating range and module is switched off. - Sleep Mode RTC runs with 32 kHz reference internally generated. Normal Operation Deep Module processor runs with 32 kHz reference generated by the internal oscillator. Idle Mode MHz reference generated by the internal oscillator. Active Mode Module processor runs with 19.2 MHz reference. Connected Mode RF Tx/Rx data connection enabled and processor core runs with 19.2 : 4 Table R4/N4 series - SARA modules operating modes definition Transition between operating modes Description Mode - powered When VCC supply is removed, the modules enter not Not Powered Module is switched off. - mode. Application interfaces are not accessible. off - powered mode, the module can enter power - When in not ). 1.6.1 mode applying VCC supply (see - off mode from active mode when the The modules enter power Module is switched off: normal shutdown by Off - Power ). off event (see 1.6.2 host processor implements a clean switch an appropriate power - - off procedure, by sending the AT+CPWROFF command or by using the PWR_ON Application interfaces are not accessible. pin (see 1.6.2 ). When in power - off mode, the modules can be switched on by the ) host processor using the PWR_ON input pin (see 1.6.1 . When in power off mode, the modules enter not - powered mode - by removing VCC supply. The modules automatically switch from the active mode to low Deep - Only the internal 32 kHz reference is active. Sleep power deep sleep mode whenever possible, upon expiration of The RF section and the application the 6 seconds AT inactivity timer, and upon expiration of “Active interfaces are temporarily disabled and Timer”, entering defined in 3GPP in the Power Saving Mode switched off: the module is temporarily not and 1.13.9 if power saving configuration is enabled (see Rel.13, ready to communicate with an external [2] R4/N4 series - , AT+CPSMS the SARA AT Commands Manual device by means of the application command). interfaces as configured to reduce the current consumption. When in low power deep sleep mode, the module switches on to the active mode upon e xpiration of “Periodic Update Timer” module enters the low power deep sleep The (see defined in 3GPP Rel.13 according to the Power Saving Mode (entering the Power Saving Mode mode AT Commands Manual [2 ] , 1.13.9 - SARA and the R4/N4 series whenever possible, if defined in 3GPP Rel.13) AT+CPSMS command), or it can be switched on to the active power saving configuration is enabled by mode by the host processor using the PWR_ON input pin (see R4/N4 - SARA AT+CPSMS command (see the section . ) 1.6.1 series AT Commands Manual [2] ), reducing 1.13.9 current consumption (see ). Power saving configuration is not enabled by default; it can be enabled by AT+CPSMS AT Commands (see the - R4/N4 series SARA [2] Manual ). System description 16029218 - R11 - UBX Page 14 of 116

15 SARA - System Integration Manual - R4/N4 series Transition between operating modes Description Mode The modules automatically switch from the active mode to low Module is switched on with application Idle mode whenever possible, upon expiration of the 6 interfaces temporarily disabled: the module power idle temporarily not ready to communicate seconds AT inactivity timer, if low power configuration is is AT C , with an external device by means of the enabled (see the SARA - ommands Manual [2] R4/N4 series AT+UPSV command). application interfaces as configured to reduce the current consumption. mode, the module switches to the active idle When in low power idle mode mode upon The module enters the low power first . The data reception over UART serial interface character received in low power idle mode wake whenever possible, if low power s up the system: it is not recognized as valid communication character, and the configuration is enabled by AT+UP SV R4/N4 series recognition of the subsequent characters is guaranteed only command (see the SARA - AT after the complete system wake - up. Commands Manual ), reducing current [2] . consumption tion is not enabled by Low power configura default; it can be enabled by AT+UPSV (see - the R4/N4 series AT Commands SARA ). Manual [2] - off mode when the The modules enter active mode from power Module is switched on with application Active interfaces enabled or not suspended: the host processor implements a clean switch - on procedure by module is ready to communicate with an using the PWR_ON pin (see ). 1.6.1 external device by means of the application The modules enter active mode from low power deep sleep mode interfaces unless power saving ), or when upon expiration of “Pe riodic Update Timer” (see 1.13.9 configuration is enabled by AT+CPSMS (see the host processor implements a clean switch on procedure by - the AT Commands R4/N4 series - SARA ). 1.6.1 using the PWR_ON pin (see ). [2] Manual off mode from active mode when the - The modules enter power - off procedure (see host processor implements a clean switch ). 1.6.2 The modules automatically switch from active to low power deep whenever possible, if power saving is enabled (see sleep mode ). 1.13.9 The module switches from active to connected mode when a RF Tx/Rx data connection is initiated or when RF Tx/Rx activity is ction previously initiated. required due to a conne The module switches from connected to active mode when a RF Tx/Rx data connection is terminated or suspended. When a data connection is initiated, the module enters RF Tx/Rx data connection is in progress. Connected connected mode from active mode. The module is prepared to accept data ice. signals from an external dev Connected mode is suspended if Tx/Rx data is not in progress. In such cases the module automatically switches from connected to active mode and then, if power saving configuration is enabled by the AT+CPSMS command, the module automatically - switches to low power deep sleep mode whenever possible. Vice versa, the module wakes up from low power deep sleep mode to ivity is active mode and then connected mode if RF Tx/Rx act necessary. When a data connection is terminated, the module returns to the active mode. - Table SARA : 5 modules operating modes description R4/N4 series - 16029218 116 of 15 Page - System description R11 UBX

16 SARA - System Integration Manual - R4/N4 series describes the transition between the different operating modes. Figure 2 Not powered Remove VCC Apply VCC Power off OFF: Switch ON: Switch • • AT+CPWROFF PWR_ON • PWR_ON If PSM mode is enabled, Incoming/outgoing data device or other dedicated if AT Inactivity Timer and expired Active Timer are communication network Deep Active Connected Sleep No RF Tx/Rx in progress, the • Upon expiration of Communication dropped Periodic Update Timer Using PWR_ON pin • is enabled, low power mode If Data received over UART is expired AT Inactivity Timer if Idle - modules operating modes transitions SARA : 2 Figure R4/N4 series - 16029218 - R11 System description UBX Page 16 of 116

17 SARA - System Integration Manual - R4/N4 series 1.5 Supply interfaces 1.5.1 Module supply input (VCC) VCC The modules must be supplied via the three pins that represent the module power supply input. rrent drawn by the R4/N4 series - SARA Voltage must be stable, because during operation, the cu modules through the VCC pins can vary by several orders of magnitude, depending on the operating and , ). 1.5.1.3 1.5.1.4 , 1.5.1.6 mode and state (as described in sections 1.5.1.2 It is important that the supply source is able to withstand both the maximum pulse current occurring during a transmit burst at maximum power level and the average current consumption occurring [1] - the SARA x call at maximum RF power level (see during Tx / R ). R4 Data Sheet pins: SARA - R412M modules provide separate supply inputs over the three VCC  VCC pi ns #52 and #53 represent the supply input for the internal RF power amplifier, demanding most of the total current drawn of the module when RF transmission is enabled during a call  agement Unit, VCC pin #51 represents the supply input for the internal baseband Power Man demanding minor part of the total current drawn of the module when RF transmission is enabled during a call The modules are internally connected each N410 - , SARA R410M - SARA 3 VCC pins of SARA - R404M , other to both the internal RF Power Amplifie r and the internal baseband Power Management Unit. 3 R4/N4 series - SARA a simplified block diagram of s provide Figure modules’ internal VCC supply routing. R410M / SARA - - R404M / R412M SARA - SARA - N410 SARA Power Power Amplifier Amplifier 53 53 VCC VCC Transceiver Transceiver 52 52 VCC VCC Power Power 51 51 VCC VCC Baseband Baseband Management Management Processor Processor Unit Unit Memory Memory : Block diagram of R4/N4 series SARA 3 modules’ internal VCC supply routing - Figure UBX ystem description 16029218 - R11 S - Page 17 of 116

18 SARA System Integration Manual R4/N4 series - - 1.5.1.1 VCC supply requirements Table 6 summarizes the requirements for the VCC modules supply. See section 2.2.1 for suggestions supply circuit compliant with the requirements listed in VCC . 6 Table to correctly design a - s R4/N4 serie ⚠ The supply circuit affects the RF compliance of the device integrating SARA modules with applicable required certification schemes as well as antenna circuit design. are fulfilled. Compliance is guar anteed if the requirements summarized in the Table 6 Requirement Remark Item voltage is VCC RF performance is guaranteed when VCC normal operating range: VCC Within nominal voltage inside the normal operating range limits. - R404M / SARA - R410M / SARA - SARA : N410 3.2 V / 4.2 V voltage VCC RF performance may be affected when is outside the normal operating range limits, though SARA - R412M: the module is still fully functional until the VCC 3.2 V / 4.5 V voltage is inside the extended operating range limits. VCC voltage during VCC voltage must be above the extended operating Within VCC extended operating range: on the module. range minimum limit to switch - normal operation : SARA - R404M / SARA - R410M / SARA - N410 The module may switch - off when the VCC voltage 3.0 V / 4.2 V drops below the extended operating range minimum - R412M: SARA limit. 3.0 V / 4.5 V extended operating range is not VCC Operation above recommended and may affect device reliability. The maximum average cur Support with adequate margin the highest rent consumption can be VCC average current greater than the specified value according to the averaged VCC current consumpti on value in actual antenna mismatching, temperature and connected mode conditions specified in the Data Sheet supply voltage. [1] SARA - R4/N4 series 1.5.1.2 Section describes current consumption profiles in connected mode. Support with adequate margin the highest peak The maximum peak Tx current consumption can be VCC peak current VCC current consumption value in Tx connected greater than the specified value according to the - actual antenna mismatching, temper ature and R4/N4 SARA mode conditions specified in the [1] supply voltage. series Data Sheet 1.5.1.2 Section describes current consumption profiles in connected mode. VCC voltage drop directly affects the RF compliance voltage drop VCC 400 mV Lower than with applicable certification schemes. during Tx slots Figure 6 voltage drop during 2G Tx VCC describes slo ts. voltage ripple High supply voltage ripple values during RF VCC Noise in the supply pins must be minimized transmissions in connected mode directly affect the during Tx RF compliance with the applicable certification schemes. - VCC - under/over under/over VCC shoot directly affects the RF Absent or at least minimized compliance with applicable certification schemes. shoot at s tart/end of Tx slots VCC describes 6 Figure shoot. - voltage under/over 6 Table : Summary of VCC modules supply requirements System description 16029218 - R11 - UBX Page 18 of 116

19 SARA - System Integration Manual - R4/N4 series VCC current consumption in LTE connected mode 1.5.1.2 R4/N4 series modules transmit and receive in half duplex mode. - SARA During an LTE connection, the The current consumption depends on output RF power, which is always regulated by the network (the current base station) s ending power control commands to the module. These power control commands are logically divided into a slot of 0.5 ms (time length of one Resource Block), thus the rate of power change can reach a maximum rate of 2 kHz. modules’ current consumption profile versus time 4 Figure shows an example of SARA - R4/N4 series frame (1 ms) according to LTE Category M1 - in connected mode: transmission is enabled for one sub half - duplex connected mode. Detailed current consumption values can be found in the . [1] Data Sheet SARA - R4/N4 series Current [mA] 500 400 300 Current consumption value depends power and on TX actual antenna load 200 100 0 1 Slot 1 Slot Time 1 Resource Block 1 Resource Block [ms] (0.5 ms) (0.5 ms) 1 LTE Radio Frame 1 LTE Radio Frame (10 ms) (10 ms) duplex connection - : VCC current consumption profile versus time during LTE Cat M1 half 4 Figure 1.5.1.3 VCC current consumption in 2G connected mode 2G consumption is determined by the current consumption profile VCC call is established, the When a typical of the 2G transmitting and receiving bursts. The current consumption peak during a transmission slot is strictly dependent on the transmitted power, which is regulated by the network. The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption. If the module is transmitting in 2G single - slot mode in the 850 or 900 MHz bands at the maximum RF er control level (approximately 2 W or 33 dBm in the Tx slot/burst), then the current consumption pow can reach a high peak / pulse (see the s (width of the μ for 576.9 ) [1] Data Sheet R4/N4 series - SARA transmit slot/burst) with a periodicity of 4.615 ms (width of 1 frame = 8 slots/burst), that is, with a 1/8 according to GSM TDMA (Time Division Multiple Access). duty cycle slot mode in the 1800 or 1900 MHz bands, the current If the module is transmitting in 2G single - consumption figures are much lower than during transmission in the low bands, due to the 3GPP output power specifications. transmitter During a call, current consumption is not significantly high while receiving or in monitor bursts, and 2G . in the bursts unused to transmit / receive it is low System description 16029218 - R11 - UBX Page 19 of 116

20 SARA R4/N4 series - System Integration Manual - 2G single Figure . slot - shows an example of the module current consumption profile versus time in 5 Current [A] 1900 mA 2.0 1.5 Peak current depends power and on TX 1.0 actual antenna load 0.5 200 mA 120 mA - 60 60 - 120 mA 40 mA - 10 0.0 unused unused MON TX unused unused RX RX unused unused unused unused TX MON unused unused Time slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot [ms] GSM frame GSM frame 4.615 ms 4.615 ms (1 frame = 8 slots) (1 frame = 8 slots) 5 : VCC current consumption profile versus time during a GSM call (1 TX slot, 1 RX slot) Figure 2G single voltage profile versus time during a VCC illustrates the 6 Figure call, according to the slot - VCC current consumption profile described in Figure 5 . related Voltage overshoot 3.8 V (typ) drop ripple undershoot unused unused MON unused unused TX unused RX unused RX unused unused TX unused unused MON slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot GSM frame GSM frame Time 4.615 ms 4.615 ms (1 frame = 8 slots) (1 frame = 8 slots) Figure slot call (1 TX slot, 1 RX slot) 2G single : Description of the VCC voltage profile versus time during a 6 - When a GPRS connection is established, more than one slot can be used to transmit and/or more than one slot can be used to receive. The transmitted power depends on network conditions, which set the peak current consumption. But according to GPRS specifications, the m aximum transmitted RF power is reduced if more than one slot is used to transmit, so the maximum peak of current is not as high as it can be in the case of a GSM call. - slot class 12, in 850 or 900 MHz bands, at maximum RF power If the module transmits in GPRS multi - level, the consumption can reach a quite a high peak but lower than the one achievable in 2G single slot mode class slot - . This happens for 2.308 ms (width of the 4 Tx slots/bursts) in the case of multi slots/bursts), so with a 1/2 duty cycle, according 12, with a periodicity of 4.615 ms (width of 1 frame = 8 to GSM TDMA. If the module is in GPRS connected mode in the 1800 or 1900 MHz bands, consumption figures are and because of the 3GPP Tx power specifications. lower than in the 850 or 900 MHz b UBX tion 16029218 - R11 System descrip - Page 20 of 116

21 SARA System Integration Manual - - R4/N4 series 7 Figure illustrates the current consumption profiles in GPRS connected mode, in 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive, as for the GPRS multi - slot class 12. Current [A] 1600 mA 1.5 Peak current depends 1.0 on TX power and actual antenna load 0.5 200mA 120mA - 60 120mA - 60 10 40mA - 0.0 unused TX MON TX TX unused MON unused RX unused TX RX TX TX TX TX Time slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot slot [ms] GSM frame GSM frame 4.615 ms 4.615 ms (1 frame = 8 slots) (1 frame = 8 slots) : VCC current consumption profile versus time during a GPRS multi 7 slot class 12 connection (4 TX slots, 1 RX slot) Figure - In case of EGPRS (i.e. EDGE) connections, the VCC current consumption profile is very similar to the - one during GPRS connections: the current consumption profile in GPRS multi slot class 12 connected d mode as slot class 12 connecte - is representative for the EDGE multi mode illustrated in the Figure 7 well. 1.5.1.4 enabled) PSM VCC current consumption in low power deep sleep mode ( mode configuration is by default disabled, but it can be enabled using the The power saving [2] AT Commands Manual SARA AT+CPSMS command (see the R4/N4 series - ). 1.13.9 and section When power saving mode is enabled, the module automatically enters the PSM low power deep sleep only mode whenever possible, reducing current consumption down to a steady value in the μ A range: kHz reference clock frequency. the RTC runs with internal 32 R4/N4 series . [1] Data Sheet - SARA Detailed current consumption values can be found in the ☞ RC turns on the crystal every ~10 s to calibrate the - Due to RTC running during PSM mode, the Cal RC oscillator, as a consequence, a very low spike in current consumption will be observed. 1.5.1.5 idle VCC current mode (low power enabled) consumption in low power mode configuration is by default disabled, but it can be enabled using the AT+UPSV idle The low power [2] ). - command (see the R4/N4 series AT Commands Manual SARA When low power mode is enabled, the module automatically enters the low power mode whenever idle the paging channel of the current base station (paging block possible, but it must periodically monitor reception), in accordance to the 2G / LTE system requirements, even if connected mode is not enabled e to by the application. When the module monitors the paging channel, it wakes up to the active mod enable the reception of the paging block. In between, the module switches to low power mode. This is known as discontinuous reception (DRX) or extended discontinuous reception (eDRX). SARA . [1] Data Sheet R4/N4 series - Detailed current consumption values can be found in the System description 16029218 - R11 - UBX Page 21 of 116

22 SARA - System Integration Manual - R4/N4 series power disabled) PSM / low VCC current consumption in active mode ( 1.5.1.6 The active mode is th e state where the module is switched on and ready to communicate with an external device by means of the application interfaces (as the USB or the UART serial interface). The module processor core is active, and the 19.2 MHz reference clock frequency is us ed. are disabled, as it is by default (see the If power saving mode and/or low power mode configuration s for details), the , +UPSV , +CPSMS [2] AT Commands Manual R4/N4 series - SARA s AT command PSM mode and/or low power mode configurations are module remains in active mode. Otherwise, if whenever possible. r mode PSM mode and/or low powe enabled, the module enters Figure illustrates a typical example of the module current consumption profile when the module is 8 case, the module is registered with the network and, while active mode is in active mode. In such maintained, the receiver is periodically activated to monitor the paging channel for paging block reception. . - SARA Detailed current consumption values can be found in the R4/N4 series Data Sheet [1] Current [mA] 100 0 Time [s] Paging period Current [mA] 100 0 Time [ms] RX Enabled ACTIVE MODE 8 : VCC current consumption Figure profile with power saving disabled and module registered with the network: active mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception 1.5.2 Generic digital interfaces supply output (V_INT) modules is generated by the module internal power output pin of the Th e V_INT - R4/N4 series SARA management circuitry when the module is switched on and it is not in the deep sleep power saving mode. The typical operating voltage is 1.8 V, whereas the current capability is specified in the SARA - R4/N4 series V_IN can be used in place of an external discrete regulator Data Sheet voltage domain . The T [1] as a reference voltage rail for external components. System description 16029218 - R11 - UBX Page 22 of 116

23 SARA - System Integration Manual - R4/N4 series System function interfaces 1.6 on 1.6.1 Module power - modules are in the not module supply is VCC powered mode (i.e. the R4/N4 series - When the SARA - not applied), they can be switched on as follows:  input pins to a valid voltage level, and then a low logic level needs to be set VCC Rising edge on the at the input pin for a valid time. PWR_ON When the - R4/N4 series modules are in the power - off mode (i.e. switched off) or in the Power SARA Saving M ode (PSM) , with a valid VCC supply applied, they can be switched on as follows: lse on the  Low pu PWR_ON pin for a valid time period The PWR_ON input pin is equipped with an internal active pull - up resistor. Detailed electrical characteristics with voltages and timings are described in the - R4/N4 series Data Sheet [1] . SARA sequence from the on powered mode, - he module switch shows t 9 - with following phases: Figure not module pins VCC The external power supply is applied to the  pin is held low for a valid time PWR_ON The   ). V_INT on of their supply source ( - stated until the switch - the generic digital pins are tri All The internal reset signal is held low: the baseband core and all digital pins are held in reset state.  When the internal reset signal is released, any digital pin is set in the correct sequence from the reset state to the default operational con uration of this phase differs within d The figured state. generic digital interfaces and USB interface due to host / device enumeration timings.  The module is fully ready to operate after all interfaces are configured. Start of interface Module interfaces Start - up configuration are configured event VCC PWR_ON RESET_N V_INT Internal Reset GPIO ON OFF System State Internal Reset Internal Reset Tristate / Floating Operational → Operational BB Pads State 0 s ~4.5 s R4/N4 series 9 : SARA - Figure switch - on sequence description recommended to monitor: ☞ ly high The Internal Reset signal is not available on a module pin, but it is SARA R4/N4 series the V_INT pin, to sense the start of the o - module switch - on sequence GPIO pin configured to provide the module operating status indication (see R4/N4 - SARA o the , AT+UGPIOC), to sense when the module is ready to operate [2] Commands Manual series interface V_INT ) of the module , no voltage - generic digital the switch Before ☞ supply ( on of the driven by an external application should be applied to any generic digital interface of the module. - SARA Before the ☞ ost application processor module is fully ready to operate, the h R4/N4 series should not send any AT command over AT communication interfaces (USB, UART) of the module. System description 16029218 - R11 - UBX Page 23 of 116

24 SAR - System Integration Manual A - R4/N4 series on routine can vary depending on the ☞ modules’ switch series R4/N4 - SARA The duration of the - / network settings and the concurrent module activities. application RESET_N ⚠ An abrupt removal of the VCC supply or forcing a low level on the input once the boot of R4/N4 series unrecoverable faulty state! modules has been triggered may lead to an - SARA 1.6.2 Module power - off can be cleanly switched off by: - R4/N4 series modules SARA AT Commands Manual R4/N4 series - SARA AT+CPWROFF command (see ).  [2] [1] Data Sheet R4/N4 series - ). pin for a valid time period (see the PWR_ON Low pulse on the  SARA - These events listed above trigger the storage of the current parameter settings in the non volatile memory of the module, and a clean network detach procedure. An abrupt under - voltage shutdown occurs on SARA - R4/N4 series modules when the VCC module supply is removed. If this occurs, it is not possible to perform the storing of the current parameter settings in the module’s non - volatile memory or to perform the clean network detach. supply during VCC R4/N4 series - SARA ☞ It is highly recommended to avoid an abrupt removal of the modules normal operations. supply during VCC An abrupt removal of the ⚠ - modules normal operations may R4/N4 series SARA lead to an unrecoverable faulty state! R4/N4 series - SARA An abrupt hardware shutdown occurs on modules when a low level is applied on RESET_N pin. In this case, the current parameter settings are not saved in the module’s non - volatile memory and a clean network detach is not performed. by It is highly recommended to avoid an hardware shutdown of the module abrupt forcing a low ☞ RESET_N input pin during module normal operation: the RESET_N he line should be set level on t low only if reset or shutdown via AT commands fails or if the module does not reply to a specific R4/N4 series AT command after a time period longer than the one defined in SARA AT Commands - Manual . [2] SARA input during RESET_N modules normal operations ⚠ Forcing a low level on the R4/N4 series - may lead to an unrecoverable faulty state! System description 16029218 - R11 - UBX Page 24 of 116

25 SARA - System Integration Manual R4/N4 series - describe the 11 Figure and - 10 Figure SARA R4/N4 series off sequence started by - modules switch input pin respectively means of the AT+CPWROFF command by means of the PWR_ON , allowing and storage of current parameter settings in the module’s non - volatile memory and a clean network detach, with the following phases:  When the +CPWROFF AT command is sent, or when a low pulse with appropr iate time duration PWR_ON [1] Data Sheet R4/N4 series starts the module input pin, ) is applied at the (see the SARA - - off routine. the switch  Then, if the +CPWROFF AT command has been sent, t he module replies OK on the AT interface: off routine is in progress. the switch - - off routine, all the digital pins are tri - the end of the switch At  voltage stated and all the internal regulators are turned off, including the generic digital interfaces supply ( ). V_INT - Then, the module remains in switch off mode as long as a switch on event does not occur (e.g.  applying a low level to V supply is removed. CC - ), and enters not PWR_ON powered mode if the OK VCC can be AT+CPWROFF removed replied by the module sent to the module VCC PWR_ON RESET_N V_INT Internal Reset ON OFF System State Tristate / Floating BB Pads State Operational → Tristate Operational 10 : R4/N4 series - Figure modules switch - off sequence by means of AT+CPWROFF command SARA The module starts VCC can be removed off routine the switch - VCC PWR_ON RESET_N V_INT Internal Reset OFF ON System State Tristate / Floating Operational Tristate -> Operational BB Pads State ~5 s ~2.5 s 0 s - by means of : off sequence switch modules - N4 series R4/ PWR_ON pin Figure 11 SARA ☞ The Internal Reset signal is not available on a module pin, but it is highly recommended to monitor V_INT h . off sequence - pin to sense the end of the switc the supply V_INT : an abrupt removal of the VCC goes low during ⚠ VCC supply can be removed only after R4/N4 series - SARA ! modules normal operations may lead to an unrecoverable faulty state off routines can largely vary switch modules’ R4/N4 series - SARA The duration of each phase in the ☞ - . module activities network settings and the concurrent application / depending on the System description 16029218 - R11 - UBX Page 25 of 116

26 SARA - System Integration Manual - R4/N4 series 1.6.3 Module reset SARA - R4/N4 series modules can be cleanly reset (rebooted) by:  ). [2] AT Commands Manual R4/N4 series - SARA AT+CFUN command (see the In the case above an “internal” or “software” reset of the module is executed: the current parameter volatile memory and a clean network detach is performed. - settings are saved in the module’s non modules when a low level is applied on SARA - An abrupt hardware shutdown occurs on R4/N4 series input pin for a valid time period. In this case, the current parameter settings are not RESET_N saved - in the module’s non volatile memory and a clean network detach is not performed. Then, the module off mode as long as a switch on event does not occur applying an appropriate low - remains in power PWR_ON input. level to the o avoid an It is highly recommended t ☞ forcing a low by hardware shutdown of the module abrupt level on the line should be set low RESET_N during modules normal operation: the input RESET_N only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the SARA - R4/N4 series AT Commands Manual [2] . ⚠ R4/N4 series - SARA input during RESET_N Forcing a low level on the modules normal operations may lead to an unrecoverable faulty state! grated directly connected to the Power Management input pin is IC, RESET_N The Unit with an inte . - up to a 1.8 V supply domain , in order to perform an abrupt hardware shutdown when asserted pull Detailed electrical characteristics with voltages and timings are described in the SARA - R4/N4 series a Sheet Dat . [1] SARA - R4/N4 Power Management Unit 1.8V Reset 18 RESET_N Shutdown 12 : RESET_N input description Figure System description 16029218 - R11 - UBX Page 26 of 116

27 - SARA - System Integration Manual R4/N4 serie s 1.7 Antenna interface interface (ANT) Antenna RF 1.7.1 SARA - R4/N4 series modules provide an RF interface for connecting the external antenna. The ANT pin represents the primary RF input/output for transmission and reception of LTE RF signals. and must be connected to the primary  The ANT pin has a nominal characteristic impedance of 50  Tx / Rx antenna through a 50 transmission line to allow clear RF transmission and reception. Antenna RF interfaces requirements 1.7.1.1 Table 7 summarizes the requirements for the antenna RF interface. See section 2.4.1 for suggestions to correctly design antennas circuits compliant with these requirements. SARA R4/N4 series ⚠ The antenna circuits affect the RF compliance of the device integrating - on schemes (for more details see section 4 ). modules with applicable required certificati Compliance is guaranteed if the antenna RF interface requirements summarized in Table 7 are fulfilled. Item Requirements Remarks Impedance The impedance of the antenna RF connection must match the 50  50  nominal characteristic impedance of the ANT port. impedance ANT The required frequency range of the antenna connected to Data R4/N4 series - SARA See the Frequency port depends on the operating bands of the used cellular module and t Range [1] Sheet he used mobile network. - The Return loss or the S S 10 dB (VSWR < 2:1) < , as the VSWR, refers to the amount of Return Loss 11 11 recommended reflected power, measuring how well the antenna RF connection  matches the 50 ANT characteristic impedance of the port. 6 dB (VSWR < 3:1) acceptable - < S 11 The impedance of the antenna termination must match as much as port over the ANT nominal impedance of the possible the 50  operating frequency range, reducing as much as possible the amount of reflected power. The radiation efficiency is the ratio of the radiated power to the fficiency 1.5 dB ( > 70% ) recommended - E > power delivered to antenna input: the efficiency is a measure of how 3.0 dB ( > 50% ) acceptable - > well an antenna receives or transmits. The radiation efficiency of the antenna connected to the ANT port needs to be enough high over the operating frequency range to Air (OTA) radiated performance - The comply with the Over - requirements, as Total Radiated Power (TRP) and the Total Isotropic itivity (TIS), specified by applicable related certification Sens schemes. The power gain of an antenna is the radiation efficiency multiplied by According to radiation exposure Maximum Gain the directivity: the gain describes how much power is transmi tted in limits the direction of peak radiation to that of an isotropic source. The maximum gain of the antenna connected to port must not ANT exceed the herein stated value to comply with regulatory agencies 4.2.2 tions . radiation exposure limits. For additional info see sec > 24 dBm ( > 0.25 W ) for R404M / The antenna connected to the ANT port must support with adequate Input Power margin the maximum power transmitted by the modules. / N410 R410M > 33 dBm ( > 2.0 W ) for R412M : Summary of Tx/Rx antenna RF interface requirements 7 Table System description 16029218 - R11 - UBX Page 27 of 116

28 SARA - System Integration Manual - R4/N4 series 1.7.2 Antenna detection interface (ANT_DET) The antenna detection is based on ADC measurement. The AN T_DET pin is an Analog to Digital Converter (ADC) provided to sense the antenna presence. The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it. The antenna detection is forced by the +UANTR AT [2] AT Commands Manual - R4/N4 series for more details on this feature. SARA command. See the SARA the pin generates a DC current (for detailed characteristics see - R4/N4 series The ANT_DET [1] Data Sheet the and measures the resulting DC voltage, thus determining the resistance from ) , the requirements to achieve to GND. So antenna connector provided on the application board antenna detection functionality are the following: in resistor (diagnostic circuit) must be used -  an RF antenna assembly with a built  an antenna detection circuit must be implemented on the application board for antenna detection circuit on application board and diagnostic circuit on antenna 2.4.2 See section - in guidelines. assembly design 1.8 SIM interface 1.8.1 SIM interface - - igh h provide modules R4/N4 series speed SIM/ME interface including automatic detection and SARA configuration of the voltage required by the connected SIM card or chip. Both 1.8 V and 3 V SIM types are supported. Activat ion and deactivation with automatic voltage switch from 1.8 VSIM 3 specifications. The - IEC 7816 - V to 3 V are implemented, according to ISO up current and protect the SIM - supply output provides internal short circuit protection to limit start to short circu its. The SIM driver supports the PPS (Protocol and Parameter Selection) procedure for baud rate - . card or chip selection, according to the values determined by the SIM SIM detection interface 1.8.2 e SIM card mechanical / physical The pin is configured as an external interrupt to detect th GPIO5 down enabled, and it can sense - presence. The pin is configured as input with an internal active pull SIM card presence only if cleanly connected to the mechanical switch of a SIM card holder as 2.5 described in section : GPIO5 Low logic level at  input pin is recognized as SIM card not present  High logic level at GPIO5 input pin is recognized as SIM card present [2] , +UGPIOC, +CIND and +CMER e details, see the SARA - R4/N4 series AT Commands Manual For mor AT commands. System description 16029218 - R11 - UBX Page 28 of 116

29 SARA - System Integration Manual - R4/N4 series communication interfaces Data 1.9 - R4/N4 series modules provide the following serial communication interface: SARA  USB interface: Universal Serial Bus 2.0 compliant interface available for the communication with a host application processor (AT commands, data, FW update by means of the FOAT feature), for See section dedicated tool and for diagnostics. FW update by means of the u blox - . 1.9.2 SPI interface: Serial Peripheral Interface available for communication with an external compatible  . 1.9.3 ee section device. S  SDIO interface: Secure Digital Input Output interface available for communication with a 1.9.4 compatible device. See section . 2 blox GNSS  DDC interface: I C bus compatible interface available for the communication with u - 2 ee section C devices. S 1.9.5 . positioning chips or modules and with external I UART interface 1.9.1 UART features 1.9.1.1 wire 1.8 V unbalanced asynchronous serial interface available on all the The UART interface is a 9 - SARA - R4/N4 series modules, supporting: 7 AT command mode  7 Data mode and Online command mode   Multiplexer protocol functionality FW upgrades by means of the FOAT feat ure (see 1.13.7 )  ☞ The UART is available only if the USB is not enabled as AT command / data communication interface: UART and USB cannot be concurrently used for this purpose. [5] T V.24 Recommendation - functionality conforming to the ITU 232 - UART interface provides RS , with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8 V for high data bit or OFF state (for electrical characteristics see the SARA - R4/N4 series Data Sheet [1] ), providing: RXD  data lines ( as output, TXD as input)  hardware flow control lines ( CTS as output, RTS as input) RI as output, DCD as output, DSR as input, as output)  modem status and control lines ( DTR - SARA R4/N4 series modules are designed to operate as cellular modems, i.e. as the data circuit - T V.24 Recommendation . A host application [5] - terminating equipment (DCE) according to the ITU UART interface represents the data terminal equipment (DTE). processor connected to the module signal names ☞ UART of the cellular modules conform to the ITU - T V.24 Recommendation [5] : e.g. line represents data transmitted by the DTE (host processor output) and received by the DCE TXD (module input). ☞ Hardware flow control is not supported by the “00”, “01” and SARA - R410M - 02B product versions, but the ON state) to communicate over UART must be set low (= RTS input line of the module “00” and “01” product versions . interface on the of the input DTR ☞ to have URCs presented over UART ON state) must be set low (= le modu interface. 7 command For the definition of the interface data mode, command mode and online mode see AT Commands SARA - R4/N4 series Manual 1] [ System description 16029218 - R11 - UBX Page 29 of 116

30 R4/N4 series SARA System Integration Manual - - SARA - R4/N4 series modules’ UART interface is by default configured in AT command mode, if the USB interface is not enabled as AT command / data communication interface (UART and USB cannot be concurrently used for this purpose): the module waits for AT command instructions and interprets all the characters received as commands to execute. All the functionalities supported by SARA - R4/N4 modules can be in general set and configured by AT commands: series [8]  AT commands according to 3GPP TS 27.007 [6] , 3GPP TS 27.005 [7] , 3GPP TS 27.010 u  ) [2] AT Commands Manual R4/N4 series - SARA blox AT commands (see the - , while the default frame format is 8N1 (8 data bits, No parity, 1 e is 115200 b/s The default baud rat N4 series SARA ). Baud rates can be configured by AT command (see the 13 Figure stop bit: see R4/ - [2] ). AT Commands Manual ☞ d rate detection and automatic frame format recognition are not supported. A utomatic bau Normal Transfer, 8N1 Possible Start of Start of 1-Byte next transfer transfer D0 D7 D6 D5 D4 D3 D2 D1 Stop Bit Start Bit (Always 0) (Always 1) = 1/( Baudrate ) t bit : Description of UART 8N1 frame format (8 data bits, no parity, 1 stop bit) 13 Figure 1.9.1.2 UART signals behavior At the end of the module boot sequence (see ), the module is by default in active mode, and 9 Figure the UART interface is initialized and enabled as AT commands interface only if the USB interface is on interface: UART and USB cannot be concurrently not enabled as AT command / data communicati used for this purpose. The configuration and the behavior of the UART signals after the boot sequence are described below:  The module data output line ( RXD ) is set by default to the OFF state (high level) a t UART in the OFF state until the module transmits some data. initialization. The module holds RXD  The module data input line ( TXD ) is assumed to be controlled by the external host once UART is initialized and if UART is used in the application. The TXD d ata input line has an internal active active R410M product versions, and an internal pull - down enabled on the “00” and SARA - B - 02 other the on enabled up pull - product version. 1.9.1.3 UART multiplexer protocol - , on the UART R4/N4 series [8] modules include multiplexer functionality as per 3GPP TS 27.010 SARA - physical link. This is a data link protocol which uses HDLC like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used physical link (UART). : virtual channels are defined The following  Channel 0: for control Multiplexer Channel 1:  DUN) data connections. UDP, - Dial Up Network (non - for all AT commands, and non TCP data socket / data call connections via relevant AT commands.  Channel 2: for Dial Up Network (DUN) data connection. It requires the host to have and use its own TCP/IP stack. The DUN can be initiated on modem side or terminal/host side. Channel 3:  blox GNSS data tunneling (not supported by “00” a - for u nd “01” product versions). System description 16029218 - R11 - UBX Page 30 of 116

31 SARA - System Integration Manual - R4/N4 series 1.9.2 USB interface 1.9.2.1 USB features - SARA Mb/s Speed USB 2.0 compliant interface with 480 - include a High modules R4/N4 series speed data with a host maximum data rate, representing the main interface for transferring high application processor, supporting : 8 AT command mode  8 Data mode and Online command mode   ) 1.13.7 ure (see FW upgrades by means of the FOAT feat  blox EasyFlash dedicated tool FW upgrades by means of the u - Trace log capture (diagnostic purposes)  USB device and can be connected to a USB host such as a Personal The module itself acts as a Computer or an embedded application microprocessor equipped with compatible drivers. The USB_D - lines carry USB serial bus data and signaling according to the Universal Serial USB_D+ / Bus Revi sion 2.0 specification [4] , while the input pin senses the VBUS USB supply VUSB_DET presence (nominally 5 V at the source) to detect the host connec tion and enable the interface. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input, which senses the USB . supply voltage and absorbs few microamperes ☞ The USB interface is available as AT command / data communication interface only if an external valid USB VBUS supply voltage (5.0 V typical) is applied at the VUSB_DET input of the module since the switch - on of the module, and then held during normal operations. In this case, the UART will be not available. ☞ If the USB interface i s enabled, the module does not enter the low power deep sleep mode: the external USB VBUS supply voltage needs to be removed from the input of the module VUSB_DET to let it enter the Power Saving Mode defined in 3GPP Rel.13 . The USB interface is controlled and operated with: [7] , 3GPP TS 27.005  AT commands according to 3GPP TS 27.007 [6] - u  - ) [2] AT Commands Manual R4/N4 series SARA blox AT commands (see the - modules can provide the following USB functions: R4/N4 series SARA The USB interface of  AT commands and data communication Diagnostic log  - The USB profile of R4/N4 series modules identifies itself by the following VID (Vendor ID) and SARA USB 2.0 uded in the USB device descriptor according to the PID (Product ID) combination, incl [4] . specifications  VID = 0x05C6 PID = 0x90B2  8 For the definition of the interface data mode, command mode and online command mode see SARA - R4/N4 series AT Commands Manual [2] System description 16029218 - R11 - UBX Page 31 of 116

32 SARA - System Integration Manual - R4/N4 series SPI interface 1.9.3 The SPI interface “02” supported by “00”, “01” is not , ☞ and “52” product versions: the SPI interface pins should not be driven by any external device. SARA - R4/N4 series modules include a Serial Peripheral Interface for communication with compatible external device. mutually exclusive way, over the The SPI interface can be made available as alternative function, in I2S_WA / SPI_MOSI I2S_CLK / SPI_CLK , , digital audio interface pins ( I2S_RXD / SPI_MISO , I2S_TXD / SPI_CS ). 1.9.4 SDIO interface supported by “00”, “ is not product versions: the SDIO 01”, “02” and “52” The SDIO interface ☞ pins should not be driven by any external device. ace interf - SARA - bit Secure Digital Input Output interface ( SDIO_D0 , SDIO_D1 , modules include a R4/N4 series 4 , and SDIO_D2 , ith external compatible ) designed to communicate w SDIO_CMD SDIO_D3 SDIO_CLK , SDIO devices . 2 1.9.5 DDC (I C) interface 2 2 ☞ C interface C interface is not supported by “00” and “01” product versions: the I pins should The I not be driven by any external device. 2 bus compatible DDC interface ( SDA C , SCL - lines ) available SARA - R4/N4 series modules include an I 2 blox GNSS receiver and with external I to communicate with a u C devices as an audio codec: the - 2 2 - R4/N4 series SARA C maste r which can communicate with I module acts as an I C slaves in 2 . C bus specifications [9] accordance with the I - and - there is no need of additional pull , so V_INT up to up resistors pins have internal pull SCL SDA The on the external application board. Audio 1.10 2 supported by “00”, “ pins should ☞ 01”, “02” and “52” ” product versions: the I Audio is not S interface not be driven by any external device. modules support VoLTE (Voice over LTE Cat M1 radio bearer) for providing audio - SARA R4/N4 series services. 2 S digital audio interface to transfer R4/N4 series modules include an I - SARA digital audio data to/from an external compatible audio device. The digital audio interface can be made available as alternative function, in mutually exclusive way, , S_TXD / I2 over the SPI interface pins ( , I2S_CLK / SPI_CLK I2S_RXD / SPI_MISO , I2S_WA / SPI_MOSI ). SPI_CS System description 16029218 - R11 - UBX Page 32 of 116

33 SARA - System Integr ation Manual - R4/N4 series 1.11 General Purpose Input/Output - SARA R4/N4 series modules include six pins (GPIO1 - GPIO6) which can be configured as General Purpose Input/Output or to provide custom functions via u - blox AT commands (for m ore details see AT Commands eries R4/N4 s - SARA the +UGPIOC, +UGPIOR, +UGPIOW AT commands), , [2] Manual as summarized in Table 8 . ion Function Descript Configurable GPIOs Default GPIO Network status Network status: registered / data transmission, no GPIO1 -- service indication 9 Enable/disable the supply of a u - blox GNSS receiver GPIO2 -- GNSS supply enable connected to the cellular module by the DDC (I2C) interface 9 Sense when a u - blox GNSS receiver connected to the -- GNSS data ready GPIO3 module is ready for sending data by the DDC (I2C) e interfac -- SIM card physical presence detection SIM card detection GPIO5 Module status Module switched off or in PSM low power deep sleep GPIO1, GPIO2, GPIO3, -- mode, versus active or connected mode GPIO4, GPIO5, GPIO6 indication 10 to trigger last gasp notification Input Last gasp -- GPIO3, GPIO4, GPIO6 GPIO1, GPIO2, GPIO3, General purpose input Input to sense high or low digital level -- GPIO4, GPIO5, GPIO6 GPIO1, GPIO2, GP IO3, General purpose output Output to set the high or the low digital level -- GPIO4, GPIO6 GPIO1, GPIO2, GPIO3, GPIO1, GPIO2, GPIO3, - Pin disabled Tri - state with an internal active pull down enabled GPIO4, GPIO5, GPIO6 GPIO4, GPIO5, GPIO6 Table 8 : SARA - R4/N4 series modules GPIO custom functions configuration 1.12 Reserved pins (RSVD) SARA - R4/N4 series modules have pins reserved for future use, marked as RSVD . All the pins are to be left unconnected on the application board, exce pt for the RSVD pin number RSVD 33 that can be externally connected to ground. 9 ot supported by “00” and “01” product versions N 10 product versions 02B - R410M - and SARA “01” , supported by “00” Not System description 16029218 - R11 - UBX Page 33 of 116

34 R4/N4 series SARA System Integration Manual - - 1.13 System features 1.13.1 Network indication GPIOs can be configured by the AT command to indicate network status (for further details see 1.11 section ): [2] AT Commands Manual R4/N4 series - SARA and the No service (no network coverage or not registered)  Registered / Data call enabled (RF data transmission / reception)  1.13.2 Antenna supervisor pin is based on an ADC measurement as ANT_DET The antenna detection function provided by the re that can be implemented if the application requires it. The antenna supervisor is optional featu R4/N4 series for more AT Commands Manual [2] - SARA forced by the +UANTR AT command (see the details). The requirements to achieve antenna detection functionality are the following: in resistor (diagnostic circuit) must be used  an RF antenna assembly with a built - an antenna detection  circuit must be implemented on the application board 2.4.2 on for detailed antenna detection interface functional description and see secti 1.7.2 See section - in for detection circuit on application board and diagnostic circuit on antenna assembly design guidelines. 1.13.3 Dual stack IPv4/IPv6 support R4/N4 series - both Internet Protocol version 4 and Internet Protocol version 6 in parallel. SARA SARA For more details about dual stack IPv4/IPv6 see the R4/N4 series - . [2] AT Commands Manual TCP/IP and UDP/IP 1.13.4 SARA - R4/N4 series modules provide embedded TCP/IP and UDP/IP protocol stack: a PDP context can be configured established and handled via the d ata connection management packet switched data commands. end - to - modules provide Direct Link mode to establish a transparent end R4/N4 series - SARA communication with an already connected TCP or UDP socket via serial inte rfaces (USB, UART). In Direct Link mode, data sent to the serial interface from an external application processor is forwarded versa. - to the network and vice R4/N4 series For more details on embedded TCP/IP and UDP/IP functionalities, see SARA AT - . [2] Commands Manual FTP 1.13.5 SARA (FTP) services. Files are read and stored provide embedded File Transfer Protocol R4/N4 series - in the local file system of the module. FTP files can also be transferred using FTP Direct Link:  FTP download : data coming from the FTP server is forwarded to the host processor via USB / UART serial interfaces (fo r FTP without Direct Link mode the data is always stored in the module’s flash file system) : data coming from the host processor via USB / UART serial interface is forwarded to  FTP upload om the module’s flash file the FTP server (for FTP without Direct Link mode the data is read fr system) System description 16029218 - R11 - UBX Page 34 of 116

35 SARA - System Integration Manual - R4/N4 series When Direct Link is used for an FTP file transfer, only the file contents passes through USB / UART serial interface, whereas all the FTP command handling is managed internally by the FTP application. AT Commands R4/N4 series - SARA ut embedded FTP functionalities, see the For more details abo [2] Manual . 1.13.6 HTTP SARA modules provide the embedded Hypertext Transfer Protocol (HTTP) services via R4/N4 series - AT commands for sending requests to a remote HTTP server, receiving the server response and tem. For more details, see the transparently storing it in the module’s flash file sys R4/N4 - SARA [2] Manual AT Commands series . Firmware update Over AT (FOAT) 1.13.7 ature allows upgrading of the module firmware over the AT interface, using AT commands. This fe The +UFWUPD AT command enables a code download to the device from the host via the Xmodem protocol. nitiates a firmware The +UFWINSTALL AT command then triggers a reboot, and upon reboot i installation on the device via a special boot loader on the module. The bootloader first authenticates the downloaded image, then installs it, and then reboots the module. Firmware authenticity verification is performed via a security s ignature. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake - up, and restarts the firmware installation. After completing the et again and wakes upgrade, the module is res up in normal boot. - - SARA For more details about Firmware update Over AT procedure, see the AT R4/N4 series [2] , +UFWUPD AT command. Commands Manual 1.13.8 Firmware update Over The Air (uFOTA) blox client/server This feature allows upgrading the module firmware over the air interface, based on u - solution (uFOTA), using LWM2M. - For more details about firmware update over AT R4/N4 series - SARA air procedure, see the - the [2] . Commands Manual Power saving 1.13.9 Guidelines to optimize power consumption 1.13.9.1 The LTE Cat technology is mainly intended for applications that only require a small M1 / NB1 amount of data exchange per day (i.e. a few bytes in uplink and downlink per day). Depending on the asons, the whole application type, the battery may be required to last for a few years. For these re application board should be optimized in terms of current consumption and should carefully take into account the following aspects: Enable the low power mode configuration using the AT+UPSV command (for the complete  - R4/N4 series AT Commands Manual [2] ). PSV command, see the description of the AT+U SARA  Enable the power saving mode configuration using the AT+CPSMS command (for the complete [2] SARA R4/N4 series ). - AT Commands Manual description of the AT+CPSMS command, see the  Use the UART interface instead of the USB interface as a serial communication interface, because the current consumption of the module is ~20 mA higher when the USB interface is enabled. Use  an application processor with a UART interface working at the same voltage level (1.8 V) as the module. In this way it is possible to avoid voltage translators, which helps to minimize current leakage. System description 16029218 - R11 - UBX Page 35 of 116

36 SARA - System Integration Manual - R4/N4 series ove the external USB VBUS voltage from the If the USB interface is implemented in the design, rem  input when serial communication is not necessary, letting the module enter the Power VUSB_DET Saving Mode defined in 3GPP Rel.13: the module does not enter the deep sleep power saving mode enabled. if the USB interface is  Minimize current leakage on the power supply line. Optimize the antenna matching, since a mismatched antenna leads to higher current  consumption.  off mode or deep sleep power saving - level to sense when the module enters power V_INT Monitor mode. ). 2.2.1.9  Disconnect the VCC supply source from the module when it is switched off (see VCC Disconnect the  p sleep power saving mode (see supply source from the module during dee can execute a 2.2.1.9 ): using a host application processor equipped with a RTC, the module volatile memory, and then rely standard PSM procedure and store the NAS protocol context in non - 11 . for running its RTC and triggering wake - on the host application processor up upon need 1.13.9.2 Functionality CPSMS command, the module automatically enters the When power saving is enabled using the AT+ 1.5.1.4 low power deep sleep mode whenever possible, reducing current consumption (see the section - [1] SARA and the ). Data Sheet R4/N4 series R4/N4 series - SARA For the definition and the description of the operating modes, including the 1.4 . events forcing transitions between the different operating modes, see section SARA The - R4/N4 series modules achieve the low power deep sleep mode by powering down all the Hardware components with the exception of the 32 kHz reference internally generated. From the host application point of view, ☞ the serial port will not be available during low power deep module will act as if it SARA - R4/N4 series sleep mode, as the is in Power - Off mode. Timers and network interaction 1.13.9.3 modules goes in low power deep sleep mode R4/N4 series - The entering in the Power Saving SARA Mode (PSM) defined in 3GPP Release 13. Two timers have been specified on the PSM Signaling: the “Periodic Update Timer” and “Active Timer” . R4/N4 series The “Active Timer” is the time defined by the network where the SARA - module will keep listening for any active operation, during this time the module is in Active mode. R4/N4 - SARA The “Periodic Update Tim er” is the Extended Tracking Area Update (TAU) used by the . series module to periodically notify the network of its availability - module requests the PSM by including the “Active Timer” with the desired The SARA series R4/N4 value in the Attach, TAU or Routing Area Update (RAU) messages. The “Active Timer” is the time the tioned from connected to active mode. When module listens to the Paging Channel after having transi the “Active Timer” expires, the module enters PSM low power deep sleep mode. SARA module can also request an extended “Periodic Update Timer” value to remain in - R4/N4 series low power deep sleep mode for longer than the original “Periodic Update Timer” broadcasted by PSM the network. - R4/N4 series module and the attached network: the The grant of PSM is a negotiation between SARA PSM by providing the actual value of the “Active Timer” (and “Periodic Update network accepts Timer”) to be used in the Attach/TAU/RAU accept procedure. The maximum duration, including the 11 saving mode power during deep sleep The use of an external RTC is not supported by the “00”, “01” and “x2” product versions U System description - 16029218 - R11 BX Page 36 of 116

37 SARA - System Integration Manual - R4/N4 series “Periodic Update Timer”, is about 413 days. The SARA module enters PSM low power R4/N4 series - deep sleep mode only after the “Active Timer” expires. Current Connected mode: Data Tx / Rx Time PSM power deep sleep mode Active mode low (periodic update timer) (active timer) Figure 14 : Description of the PSM timing 1.13.9.4 Timers and AT interaction the Power Saving Mode The SARA - R4/N4 series modules go in to low power deep sleep mode and enter : (PSM) only after the 6 s “AT Inactivity Timer” expires If the UART interface is used, the – T commands for 6 s sending A s  the host application stop when “AT Inactivity Timer” expiration – deep sleep power saving mode according s then the module enter to “Active Timer” expiration . . If the USB interface is enabled, the module does not enter the deep sleep power saving mode  s AT command 1.13.9.5 The module uses the +CPSMS AT command with its defined parameters to request PSM timers to the network. ☞ [2] R4/N4 series for details of the +CPSMS operation and - AT Commands Manual See the SARA features. 1.13.9.6 Host application The PSM low power deep sleep mode implementation allows the SARA - R4/N4 series module to help extend the battery life of the application. - SARA The Host Application should be aware that the capable. - module is PSM R4/N4 series supply output of the module to get the notification V_INT ☞ The host application needs to sense the en the module has entered into PSM low power deep sleep mode. wh R4/N4 series - SARA ☞ If the host application receives an event that needs to be reported by the module interrupting the PSM low power deep sleep mode, it can be done so by setting the module ). 1.6.1 on event (see - into Active mode using the appropriate power ☞ From the host application point of view, the module will look as it is in Power - Off mode. Normal operation 1.13.9.7 module to transition from PSM low power deep - SARA The Host Application can force the R4/N4 series - sleep mode to Active mode by using the Power Up procedure specifie d in section 1.6.1 . ☞ Be aware that when the host application transitions from low power deep sleep mode to active mode, it will cause the module to consume the same amount of power as in - R4/N4 series SARA active mode, thereby shortening the battery life of the host application. System description 16029218 - R11 - UBX Page 37 of 116

38 SARA - System Integration Manual - R4/N4 series in - Design 2 2.1 Overview modules in the final application board, follow the R4/N4 series - For an optimal integration of the SARA design guidelines stated in this section. Every application circuit must be suitably designed to guarantee the correct functionality of the relative interface, but a of the number of points require particular attention during the design . application device provides a rank of importance in the application design, starting from the highest The following list relevance: Module antenna connection: 1. ANT and ANT_DET pins. R4/N4 series - SARA tenna circuit directly affects the RF compliance of the device integrating a An module with applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the schematic and layout design. and pins. GND 2. Module supply: VCC - SARA The supply circuit affects the RF compliance of the device integrating a R4/N4 series module with the applicable required certification schemes as well as the antenna circuit design. for the schematic and 2.2.1 Very carefully follow the suggestions provided in the relative section layout design. 3. pins. VUSB_DET and - USB_D , USB_D+ USB interface: - speed interface functionality. Carefully Accurate design is required to guarantee USB 2.0 high 2.6 follow the sug gestions provided in the relative section .2 for the schematic and layout design. , SIM_IO , SIM_CLK SIM interface: , VSIM pins. SIM_RST 4. Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling. Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design. pins. PWR_ON and RESET_N System functions: 5. Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully follow the suggestio ns provided in relative section 2.3 for schematic and layout design. 2 2 Other digital interfaces: UART, SPI, SDIO, I C, I S, GPIOs and reserved pins. 6. Accurate design is required to guarantee correct functionality and reduce the risk of digital data 2.6.2 , 2.6.1 , 2.6.3 , 2.6.4 , frequency harmonics coupling. Follow the suggestions provided in sections , 2.6.5 , 2.8 and 2.9 for the schematic and layout design. 2.7 Other supplies: 7. V_INT generic digital interfaces supply. Accurate design is required to guarantee correct functionality. Follow the suggestions provided in the corresponding section for the schematic and layout design. 2.2.2 It is recommended to follow the specific design guidelines provided by each manufacturer of any ☞ blox cellular modules. external part selected for the application board integrating the u - - in 16029218 - R11 Design - UBX Page 38 of 116

39 SARA - System Integration Manual - R4/N4 series Supply interfaces 2.2 Module supply (VCC) 2.2.1 2.2.1.1 General guidelines for VCC supply circuit selection and design supply minimizing the power loss due VCC All the available pins have to be connected to the external to series resistance. pins are internally connected. Application design shall connect all the available pads to solid GND ground on the application board, since a good (low impedance) connection to external ground can inimize power loss and improve RF and thermal performance. m - pins with a suitable DC power supply VCC modules must be sourced through the R4/N4 series SARA requirements VCC dules’ that should meet the following prerequisites to comply with the mo Table 6 . summarized in The appropriate DC power supply can be selected according to the application requirements (see ) between the different possible supply sources types, which most common ones are the 15 Figure following:  Switching regulator  - regulator Out (LDO) linear Low Drop ion polymer (Li  Rechargeable Lithium - ion (Li Pol) battery - - - Ion) or Lithium  Primary (disposable) battery No, portable device Battery Main Supply - Ion 3.7 V Li Available? Yes, always available Linear LDO Main Supply No, less than 5 V Regulator Voltage > 5V? Yes, greater than 5 V - Switching Step Down Regulator Figure 15 : VCC supply concept selection The switching step down regulator is the typi cal choice when primary supply source has a nominal - SARA - R4/N4 series . voltage much higher (e.g. greater than 5 V) than the operating supply voltage of down provides the best power efficiency fo The use of switching step - r the overall application and minimizes current drawn from the main supply source. See section 2.2.1.2 for design - in. The use of an LDO linear regul ator becomes convenient for a primary supply with a relatively low voltage (e.g. less or equal than 5 V). In this case, the typical 90% efficiency of the switching regulator diminishes the benefit of voltage step ut current savings. down and no true advantage is gained in inp - down as they - On the opposite side, linear regulators are not recommended for high voltage step 2.2.1.3 in. - for design dissipate a considerable amount of energy in thermal power. See section modules are deployed in a mobile unit where no permanent primary supply R4/N4 series - SARA If - cell Li - Ion or Li - VCC source is available, then a battery will be required to provide . A standard 3 Pol - is the usual choice for battery VCC battery pack directly connected to powered devices. During MH chemistry typically reach a maximum voltage that is above the charging, batteries with Ni - , maximum rating for VCC , and should therefore be avoided. See sections and 2.2.1.6 2.2.1.4 , 2.2.1.5 in. 2.2.1.7 for specific design - Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger circuit, which is not included in the modules. The charger circuit needs to be designed to prevent over - UBX i 16029218 - R11 Design - - n Page 39 of 116

40 R4/N4 series SARA System Integration Manual - - pins, and it should be selected according to the application requirements. A DC/DC VCC voltage on switching charger is the typical choice when the charging source has a high nominal voltage (e.g. ~ ource has a relatively low V), whereas a linear charger is the typical choice when the charging s 12 nominal voltage (~5 V). If both a permanent primary supply / charging source (e.g. ~12 V) and a - up battery (e.g. 3.7 V Li - Pol) are available at the same time as possible supply rechargeable back regulator with integrated power path management function can be source, then a suitable charger / selected to supply the module while simultaneously and independently charging the battery. See 2.2.1.7 in. - for specific design and sections 2.2.1.6 An appropriate primary (not rechargeable) battery can be selected taking into accou nt the maximum current specified in the during connected mode, considering that [1] Data Sheet R4/N4 series - SARA 2.2.1.5 in. - for specific design primary cells might have weak power capability. See section The usage of more than one DC supply at the same time s hould be carefully evaluated: depending on the supply source characteristics, different DC supply systems can result as mutually exclusive. The selected regulator or battery must be able to support with adequate margin the highest averaged current consumption value specified in the . [1] SARA R4/N4 series - Data Sheet The following sections highlight some design aspects for each of the supplies listed above providing VCC in compliant with the module - application circuit design . 6 Table requirements summarized in 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator The use of a switching regulator is suggested when the difference from t he available supply rail source VCC to the value is high, since switching regulators provide good efficiency transforming a 12 V or supply. VCC greater voltage supply to the typical 3.8 V value of the The characteristics of the switching regulator connecte d to pins should meet the following VCC VCC : 6 Table requirements summarized in prerequisites to comply with the module  Power capability : the switchin g regulator with its output circuit must be capable of providing a pins within the specified operating range and must be capable of voltage value to the VCC pins the maximum current consumption occurring during transmissions at the VCC delivering to . [1] Data Sheet R4/N4 series - SARA m power, as specified in the maximu  : the switching regulator together with its output circuit must be capable of Low output ripple VCC voltage profile. providing a clean (low noise) for best performance and for smaller applications it is recommended High switching frequency:  to select a switching frequency 600 kHz (since L - C output filter is typically smaller for high ≥ switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce VCC oise in the profile and therefore negatively impact modulation spectrum performance. n  PWM mode operation : it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in connected mode, the Pulse Frequency Modulation (PFM) mode an d PFM/PWM VCC modes transitions must be avoided to reduce noise on voltage profile. Switching regulators can be used that are able to switch between low ripple PWM mode and high ripple PFM mode, ges status from the active mode provided that the mode transition occurs when the module chan to connected mode. It is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold. - in 16029218 - R11 Design - UBX Page 40 of 116

41 SARA System Integration Manual - R4/N4 series - Table s listed in component 9 and the show an example of a high reliability power supply Figure 16 circuit for the SARA R412M modules that support 2G radio access technology. This circuit is also - suitable for the other - input is supplied by a step modules, where the module VCC R4/N4 series - SARA down switching regulator capable of delivering the highest peak / pulse current specified for the 2G frequency in PWM mode operation greater case, with low output ripple and with fixed switching - use than 1 MHz. 12V SARA - R4/N4 4 VIN 51 VCC 1 5 BD 52 R1 RUN VCC 53 C6 2 9 VCC BOOST VC L1 3 10 RT SW C8 C10 C9 C11 D1 U1 7 R4 PG R3 R2 6 8 FB SYNC C7 GND C4 C5 C2 C3 C1 R5 GND 11 modules - down regulator N4 series R4/ SARA : Example of high reliability VCC supply circuit for 16 Figure - , using a step Description - Part Number Reference Manufacturer 10 μ F Capacitor Ceramic X7R 5750 15% 50 V Generic manufacturer C1 Generic manufacturer 10 nF Capacitor Ceramic X7R 0402 10% 16 V C2 680 pF Capacitor Ceramic X7R 0402 10% 16 V Generic manufacturer C3 C4 22 pF Capacitor Ceramic C0G 0402 5% 25 V Generic manufacture r 10 nF Capacitor Ceramic X7R 0402 10% 16 V C5 Generic manufacturer C6 Generic manufacturer 470 nF Capacitor Ceramic X7R 0603 10% 25 V C7 T520B107M006ATE015 – Kemet 100 μ F Capacitor Tantalum B_SIZE 20% 6.3V 15m  C8 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata C9 C10 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata C11 Murata - GRM1555C1E150JA01 15 pF Capacitor Ceramic C0G 0402 5% 50 V D1 Schottky Diode 40 V 3 A MBRA340T3G ON Semiconductor - 10 L1 744066100 Wurth Electronics - H Inductor 744066100 30% 3.6 A μ R1 Generic manufacturer 470 k  Resistor 0402 5% 0.1 W Generic manufacturer R2 15 k  Resistor 0402 5% 0.1 W Generic manufacturer R3 22 k Resistor 0402 5% 0.1 W  Generic manufacturer R4 Resistor 0402 1% 0.063 W 390 k  Generic manufacturer R5  Resistor 0402 5% 0.1 W 100 k Step - Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology U1 Table down regulator modules R4/N4 series - - SARA s for high reliability VCC supply circuit for : Component 9 , using a step , for the parts recommended to be 19 Table / 27 Figure , and in particular 2.2.1.10 section ☞ See the provided if the application device integra tes an internal antenna. - in 16029218 - R11 Design - UBX Page 41 of 116

42 SARA - System Integration Manual - R4/N4 series and the components listed in show an example of a high reliability power sup 10 Table ply 17 Figure N410 , SARA R410M - R404M - modules, which do not support the 2G radio circuit for SARA - and SARA down switching regulator access technology. In this example, the module VCC is supplied by a step - ed for the LTE use - case, with low capable of delivering the maximum peak / pulse current specifi output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. R404M - SARA 12V R410M - SARA SARA N410 - 2 3V8 51 VCC VCC 1 9 EN VCC 52 VSW L1 53 VCC R1 D1 C3 C8 C7 C6 C9 10 8 BST PG U1 C2 C1 5 FB C4 C5 R2 GND PGND GND 4 11 - - - N410 R410M / , using a step Figure 17 : Example of high reliability VCC supply circuit for SARA - R404M / down regulator Description Reference - Part Number Manufacturer C1 10 μ F Capacitor Ceramic X7R 50 V Generic manufacturer C2 10 nF Capacitor Ceramic X7R 16 V Generic manufacturer manufacturer Generic 22 nF Capacitor Ceramic X7R 16 V C3 C4 22 μ F Capacitor Ceramic X5R 25 V Generic manufacturer C5 22 μ F Capacitor Ceramic X5R 25 V Generic manufacturer GRM155R71C104KA01 C6 100 nF Capacitor Ceramic X7R 16 V - Murata C7 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata C8 GRM1555C1E150JA01 Murata - C9 15 pF Capacitor Ceramic C0G 0402 5% 50 V MBR230LSFT1G - ON Semiconductor D1 Schottky Diode 30 V 2 A L1 TDK - PF - 4R7M2R0 - SLF7045T H Inductor 20% 2 A μ 4.7 R1 Generic manufacturer 470 k  Resistor 0.1 W Generic manufacturer R2  Resistor 0.1 W 150 k Down Regulator 1 A 1 MHz Step - U1 TS30041 - Semtech / R404M - for SARA down regulator components igh reliability VCC supply circuit H : 10 Table , using a step N410 - / - R410M - , and in particular 19 Table / 27 , for the parts recommended to be 2.2.1.10 section See the ☞ Figure provided if the application device integra tes an internal antenna. - in 16029218 - R11 Design - UBX Page 42 of 116

43 SARA - System Integrati on Manual - R4/N4 series 11 able T show an example of a low cost power supply circuit and the components listed in 18 Figure modules, VCC where the module R4/N4 series - SARA suitable for all the is supplied by a step - down switching regulator capable of delivering the highest peak / pulse current specified for the 2G use - case, transforming a 12 V supply input. 12V SARA - R4/N4 8 VCC 51 VCC 1 3 OUT 52 INH VCC L1 53 VCC R3 D1 R1 C10 C7 C8 C9 C3 U1 6 5 FSW FB C4 C2 C1 R4 2 4 SYNC COMP C6 GND R5 R2 GND C5 7 R4/N4 series SARA down regulator - - : Example of low cost VCC supply circuit for 18 Figure , using a step modules Part Number Manufacturer - Description Reference C1 Generic manufacturer F Capacitor Ceramic X5R 1210 10% 25 V μ 22 C2 Generic manufacturer 220 nF Capacitor Ceramic X7R 0603 10% 25 V Generic manufacturer X7R 0402 10% 50 V 5.6 nF Capacitor Ceramic C3 Generic manufacturer 6.8 nF Capacitor Ceramic X7R 0402 10% 50 V C4 56 pF Capacitor Ceramic C0G 0402 5% 50 V Generic manufacturer C5 C6 T520B107M006ATE015 Kemet –  F Capacitor Tantalum B_SIZE 20% 6.3V 15m μ 100 C7 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata - Murata GRM155R71C103KA01 10 nF Capacitor Ceramic X7R 16 V C8 - 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 Murata C9 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 - Murata C10 – STMicroelectronics Schottky Diode 25V 2 A STPS2L25 D1 Coilcraft – - MSS1038 522NL L1 5.2 μ H Inductor 30% 5.28A 22 m  R1 Generic manufacturer Resistor 0402 1% 0.063 W  4.7 k R2 manufacturer Generic Resistor 0402 1% 0.063 W 910  Generic manufacturer R3 Resistor 0402 5% 0.063 W 82  Generic manufacturer R4  Resistor 0402 5% 0.063 W 8.2 k R5 Generic manufacturer Resistor 0402 5% 0.063 W  39 k - L5987TR – ST Microelectronics VFQFPN 3 A 1 MHz U1 Step - Down Regulator 8 modules, R4/N4 series - - SARA : Suggested components for low cost VCC circuit for 11 able T down regulator using a step , for the parts recommended to be 19 Table / 27 Figure , and in particular 2.2.1.10 section ☞ See the provided if the application device integra tes an internal antenna. - in 16029218 - R11 Design - UBX Page 43 of 116

44 SARA System Integration Manual R4/N4 series - - Guidelines for VCC supply circuit design using o - rop low d 2.2.1.3 ut linear regulator The use of a linear regulator is suggested when the difference from the available supply rail source and the ide high efficiency when transforming a 5 VDC value is low. The linear regulators prov VCC supply to a voltage value within the module VCC normal operating range. The characteristics of the Low Drop Out (LDO) linear regulator connected to VCC pins should meet - the following prerequisites to comply wit : 6 Table requirements summarized in VCC h the module Power capabilities  : the LDO linear regulator with its output circuit must be capable of providing a VCC voltage value to the pins within the specified operating range and must be capable of pins the maximum current consumption occurring during a transmission at the VCC delivering to . [1] Data Sheet R4/N4 series - SARA maximum Tx power, as specified in the  Power dissipation : the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the rated range (i.e. check the voltage drop from the maximu m input voltage to the minimum output voltage to evaluate the power dissipation of the regulator). Figure 19 and the components listed in Table 12 show an example of a high reliability power supply circuit for the SARA - R412M modules supporting the 2G radio access technology. This example is also modules, module VCC where the supply is provided by an R4/N4 series sui - SARA table for the other - LDO linear regulator capable of delivering the highest peak / pulse current specified for the 2G use power handling capability. The regulator described in this example supports case, with an appropriate a wide input voltage range, and it includes internal circuitry for reverse battery protection, current limiting, thermal limiting and reverse current protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit 20 and ). This reduces the power on the linear regulator and improves the Figure described in 13 Table whole thermal design of the supply circuit. SARA R4/N4 - 5V 51 VCC 4 2 IN 52 OUT VCC 53 VCC U1 R1 C3 C6 C4 C5 1 5 SHDN ADJ C1 C2 GND GND R2 3 Figure 19 : Example of hi gh reliability VCC supply circuit for SARA - R4/N4 series modules , using an LDO linear regulator Reference Description Part Number - Manufacturer 10 Generic manufacturer F Capacitor Ceramic X5R 0603 20% 6.3 V C1 μ T520B107M006ATE015 – Kemet C2 μ 100  F Capacitor Tantalum B_SIZE 20% 6.3V 15m 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata C3 C4 10 nF Capacitor Ceramic X7R 16 V GRM155R71C103KA01 - Murata GRM1555C1E680JA01 Murata - C5 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E150JA01 C6 15 pF Capacitor Ceramic C0G 0402 5% 50 V Murata - Generic manufacturer R1  9.1 k Resistor 0402 5% 0.1 W R2 Generic manufacturer  3.9 k Resistor 0402 5% 0.1 W Linear Technology - LT1764AEQ#PBF LDO Linear Regulator ADJ 3.0 A U1 Table , using an LDO regulator modules R4/N4 series - SARA : Suggested components for high reliability VCC circuit for 12 - in 16029218 - R11 Design - UBX Page 44 of 116

45 SARA - System Integration Manual - R4/N4 series , for the parts recommended to be 19 ☞ See the section 2.2.1.10 , and in particular Figure 27 / Table provided if the application device integrates an internal antenna. and the components listed in Figure 20 Table 13 show an example of a high reliability power supply modules, which do not support the 2G radio circuit for SARA - R404M , SARA - R410M and SARA - N410 access technology, where the module is supplied by an LDO linear regulator capable of delivering VCC e - case, with suitable power handling capability. maximum peak / pulse current specified for LTE us It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly normal operating range (e.g. ~4.1 V for the below the maximum limit of the module VCC VCC , as in the ts described in reduces the power on the linear regulator and circui ). This Figure 20 and Table 13 improves the thermal design of the circuit. SARA - R404M R410M SARA - - SARA N410 5V 51 VCC 1 8 IN OUT 52 VCC 53 VCC U1 R1 R2 C4 C5 C6 C3 5 3 ADJ EN C1 C2 GND GND R3 4 / R404M - : Example of high reliability VCC supply circuit for SARA 20 Figure regulator , using an LDO linear N410 - / R410M - Reference Description Part Number - Manufacturer F Capacitor Ceramic X5R 6.3 V C1 1 μ Generic manufacturer C2 22 μ F Capacitor Ceramic X5R 25 V Generic manufacturer Murata C3 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - GRM155R71C103KA01 Murata Capacitor Ceramic X7R 16 V 10 nF C4 - C5 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata C6 Murata - GRM1555C1E150JA01 15 pF Capacitor Ceramic C0G 0402 5% 50 V R1 Generic manufacturer 47 k  Resistor 0.1 W R2 Generic manufacturer  Resistor 0.1 W 41 k R3 Generic manufacturer 10 k  Resistor 0.1 W U1 LDO Linear Regulator 1.0 A AP7361 – Diodes Incorporated / R410M - R404M / - SARA : Components for high reliability VCC supply circuit for 13 Table , using an LDO linear regulator N410 - , for the parts recommended to be 19 Table / 27 Figure , and in particular 2.2.1.10 section See the ☞ provided if the application device integrates an interna l antenna. - in 16029218 - R11 Design - UBX Page 45 of 116

46 SARA - System Integration Manual - R4/N4 series uit, show an example of a low cost power supply circ 14 Table and the components listed in Figure 21 where the supply is provided by an LDO linear regulator capable of delivering the specified module VCC highest peak / pulse current, with an appropriate power handling capability. The regulator described e range and it includes internal circuitry for current and in this example supports a limited input voltag thermal protection. It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range (e.g. ~4.1 V as in the circuit 21 Figure described in ). This reduces the power on the linear regulator and improves the 14 Table and who le thermal design of the supply circuit. - SARA R4/N4 5V 51 VCC 4 2 IN OUT 52 VCC 53 VCC U1 R1 C6 C4 C5 C3 1 5 EN ADJ C1 C2 GND GND R2 3 R4/N4 series modules , using an LDO linear regulator SARA : Example of low cost VCC supply circuit for 21 Figure - Manufacturer - Part Number Description Reference F Capacitor Ceramic X5R 0603 20% 6.3 V μ 10 C1 Generic manufacturer – Kemet C2 T520B107M006ATE015 F Capacitor Tantalum B_SIZE 20% 6.3V 15m μ 100  Murata C3 100 nF Capacitor Ceramic X7R 16 V GRM155R71C104KA01 - Murata - GRM155R71C103KA01 nF Capacitor Ceramic X7R 16 V 10 C4 C5 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1E680JA01 - Murata - GRM1555C1E150JA01 C6 15 pF Capacitor Ceramic C0G 0402 5% 50 V Murata Generic manufacturer R1 Resistor 0402 5% 0.1 W  27 k Generic manufacturer R2 4.7 k  Resistor 0402 5% 0.1 W LDO Linear Regulator ADJ 3.0 A U1 LP38501ATJ - ADJ/NOPB - Texas Instrument R4/N4 - SARA near regulator : Suggested components for low cost VCC supply circuit for 14 Table modules , using an LDO li .1.10 , and in particular 19 Table / 27 Figure ☞ , for the parts recommended to be 2.2 section See the tes an internal antenna. provided if the application device integra - in 16029218 - R11 Design - UBX Page 46 of 116

47 ARA S - System Integration Manual - R4/N4 series 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery - pins should meet the following Ion or Li VCC Pol batteries connected to the Rechargeable Li - Table in requirements summarized VCC prerequisites to comply with the module : 6  Maximum pulse and DC discharge current : the rechargeable Li - Ion battery with its related output pins must be circuit connected to the capable of delivering the maximum current occurring VCC - SARA during a transmission at maximum Tx power, as specified in the Data R4/N4 series Sheet [1] . The maximum discharge current is not always reported in the data sheets of batteries, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp - ded by 1 hour. hours divi -  Ion battery with its output circuit must be capable of : the rechargeable Li DC series resistance avoiding a VCC voltage drop below the operating range summarized in during transmit 6 Table bursts. Guidelines for VCC supply circuit design using a primary battery 2.2.1.5 rechargeable) battery connected to pins should meet the The characteristics of a primary (non - VCC following prerequisites to comply with the module : 6 Table requirements summarized in VCC - rechargeable battery with its related output : the non Maximum pulse and DC discharge current  pins must be capable of delivering the maximum current VCC circuit connected to the R4/N4 consumption occurring during a transmission at maximum Tx power, as specified in SARA - series Data Sheet [1] . The maximum discharge current is not always reported in the data sheets current is typically almost equal to the battery of batteries, but the maximum DC discharge hours divided by 1 hour. capacity in Amp - DC series resistance : the non - rechargeable battery with its output circuit must be capable of  Table avoiding a VCC voltage drop below the operating range summarized in 6 during transmit bursts. Guidelines for external battery charging circuit 2.2.1.6 board charging circuit. R4/N4 series 22 Figure provides an example - modules do not have an on - SARA powered with a Li of a battery charger design, suitable for applications that are battery - Ion (or Li - Polymer) cell. Polymer) battery cell, that features the correct - In the application circuit, a rechargeable Li - Ion (or Li pulse and DC discharge current capabilities and the appropriate DC series resistance, is directly ed to the VCC connect supply input of the module. Battery charging is completely managed by the Battery Charger IC, which from a USB power source (5.0 V typ.), linearly charges the battery in three phases: - (active when the battery is de Pre  eply discharged): the battery is charge constant current charged with a low current.  Fast - charge constant current : the battery is charged with the maximum current, configured by the value of an external resistor. Constant voltage tput voltage, the Battery  : when the battery voltage reaches the regulated ou Charger IC starts to reduce the current until the charge termination is done. The charging process ends when the charging current reaches the value configured by an external resistor or when the charging timer reaches the factory set value. Using a battery pack with an internal NTC resistor, the Battery Charger IC can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions. - in 16029218 - R11 Design - UBX Page 47 of 116

48 SARA - System Integration Manual - R4/N4 series applications where the charging source The Battery Charger IC, as linear charger, is more suitable for has a relatively low nominal voltage (~5 V), so that a switching charger is suggested for applications for the 2.2.1.7 where the charging source has a relatively high nominal voltage (e.g. ~12 V, see section in). - specific design - Li Ion/Li - Polymer R4/N4 - SARA Battery Charger IC 5V0 USB Vbat VDD 51 VCC Supply Pol - Ion/Li - Li 52 VCC Battery Pack C2 53 VCC PG THERM C1 θ STAT2 PROG C5 C4 C3 C6 R1 B1 STA1 Vss GND D1 D2 U1 - : Li 22 Figure - Ion (or Li Polymer) battery charging application circuit Description Part Number - Manufacturer Reference Generic manufacturer B1 Polymer) battery pack with 470 - Ion (or Li - Li NTC  μ F Capacitor Ceramic X7R 16 V C1 Generic manufacturer 1 C2 Kemet – T520B107M006ATE015 μ F Capacitor Tantalum B_SIZE 20% 6.3V 15m  100 Murata - GRM1555C1H150JA01 C3 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 C4 68 pF Capacitor Ceramic C0G 0402 5% 50 V - Murata - Murata GRM155R71C103KA01 C5 10 nF Capacitor Ceramic X7R 0402 10% 16 V - GRM155R71C104KA01 C6 0402 10% 16 V 100 nF Capacitor Ceramic X7R Murata - CG0402MLE Low Capacitance ESD Protection - 18G D1, D2 Bourns R1 Generic manufacturer 10 k  Resistor 0.1 W Polymer) Battery Charger IC Microchip - MCP73833 - Ion (or Li - U1 Single Cell Li Ion (or Li - 15 Table : Suggested components for the Li Polymer) battery charging application circuit - Table , for the parts recommended to be 27 Figure in particular , and 2.2.1.10 section See the / ☞ 19 provided if the application device integrates an internal antenna. Guidelines for external charging and power path management circuit 2.2.1.7 re both a permanent primary supply / charging source (e.g. ~12 V) and a Application devices whe - up battery (e.g. 3.7 V Li Pol) are available at the same time as a possible supply - rechargeable back management source, should implement a suitable charger / regulator with integrated power path function to supply the module and the whole device while simultaneously and independently charging the battery. ied block diagram circuit showing the working principle of a charger / Figure 23 reports a simplif regulator with integrated power path management function. This component allows the system to be powered by a permanent primary supply source (e.g. ~12 V) using the integrated regulator , which - simultaneously and independently recharges the battery (e.g. 3.7 V Li - Pol) that represents the back up supply source of the system. The power path management feature permits the battery to supply source is not available or supplement the system current requirements when the primary cannot deliver the peak system currents. - in 16029218 - R11 Design - UBX Page 48 of 116

49 SARA - System Integration Manual - R4/N4 series VCC A power management IC should meet the following prerequisites to comply with the module Table requirements summarized in : 6 as indicated 2.2.1.2 in section characteristics High efficiency internal step down converter, with   Vbat, typically lower than 50 m  Low internal resistance in the active path Vout –  High efficiency switch mode charger with separate power path control Power path management IC System 12 V Vout Vin Primary Source DC/DC converter and battery FET control logic - Pol - Li Ion/Li Battery Pack Vbat Charge controller θ GND GND : Charger / regulator with 23 Figure integrated power path management circuit block diagram 24 Figure provide an application circuit example where the MPS Table and the parts listed in 16 MP2617H switching charger / regulator with integrated power path management function provides the supply to the cellular module. At the same time it also concurrently and autonomously charges a - and DC discharge current capabilities and Polymer) battery with the correct pulse suitable Li - Ion (or Li the appropriate DC series resistance according to the rechargeable battery recommendations 2.2.1.4 described in section . The MP2617H IC constantly monitors the battery voltage and selects whether to use the external main primary supply / charging source or the battery as supply source for the module, and starts a charging phase accordingly. The MP2617H IC no rmally provides a supply voltage to the module regulated from the external main primary source allowing immediate system operation even under missing or deeply discharged - battery: the integrated switching step output current down regulator is capable to provide up to 3 A with low output ripple and fixed 1.6 MHz switching frequency in PWM mode operation. The module load is satisfied in priority, then the integrated switching charger will take the remaining current to charge the battery. er path control allows an internal connection from battery to the module with a Additionally, the pow  low series internal ON resistance (40 m typical), in order to supplement additional power to the or when this module when the current demand increases over the external main primary source external source is removed. Battery charging is managed in three phases: (active when the battery is deeply discharged): the battery is Pre - charge constant current  charge current charged with a low current, set to 10% of the fast -  Fast - charge constant current : the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for the application  Constant voltage : when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively reduced until the charge termination is done. The charging process ends - charge current or when the charging timer when the charging current reaches the 10% of the fast reaches the value configured by an external capacitor - in 16029218 - R11 Design - UBX Page 49 of 116

50 SARA System Integration Manua l - R4/N4 series - ack with an internal NTC resistor, the MP2617H can monitor the battery temperature Using a battery p to protect the battery from operating under unsafe thermal conditions. Several parameters as the charging current, the charging timings, the input current limit, the input oltage limit, the system output voltage can be easily set according to the specific application v requirements, as the actual electrical characteristics of the battery and the external supply / charging source: suitable resistors or capacitors must be accord ingly connected to the related pins of the IC. Ion/Li - Li - Polymer Battery Charger / Regulator with Power Path Managment BST C4 12V L1 - SARA R4/N4 Primary VIN SW Source D3 R4 51 VCC 52 SYS VLIM VCC + 53 VCC SYSFB Pol - Ion/Li - Li R6 C5 R5 Battery Pack R7 ENn BAT R1 ILIM NTC C10 C12 C13 C11 R2 θ ISET VCC R3 TMR GND C8 C7 C3 C6 D1 D2 B1 AGND PGND C1 C2 U1 Figure 24 : Li - Ion (or Li - Polymer) battery charging and power path management application circuit - Reference Description Part Number Manufacturer B1 Various manufacturer Ion (or Li - -  NTC Li Polymer) battery pack with 10 k GRM32ER61E226KE15 F Capacitor Ceramic X5R 1210 10% 25 V μ 22 Murata - C1, C6 Murata C2, C4, C10 100 nF Capacitor Ceramic X7R 0402 10% 16 V - GRM155R61A104KA01 C3 Murata - GRM188R71E105KA12 ic X7R 0603 10% 25 V F Capacitor Ceram μ 1 C5 T520D337M006ATE045 - KEMET 330 μ F Capacitor Tantalum D_SIZE 6.3 V 45 m  GRM1555C1H680JA01 - C7, C12 68 pF Capacitor Ceramic C0G 0402 5% 50 V Murata C8, C13 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - Murata Murata C11 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - CG0402MLE Low Capacitance ESD Protection D1, D2 Bourns - 18G - Schottky Diode 40 V 3 A MBRA340T3G - D3 ON Semiconductor R1, R3, R5, R7 Generic manufacturer  10 k Resistor 0402 1% 1/16 W R2 Generic manufacturer 1.05 k Resistor 0402 1% 0.1 W  R4 Generic manufacturer 22 k  Resistor 0402 1% 1/16 W Generic manufacturer R6 Resistor 0402 1% 1/16 W  26.5 k SRN8040 L1 Bourns 2R2Y - - 2.2 20%  H Inductor 7.4 A 13 m μ Polymer Battery DC/DC Charger / Regulator Ion/Li - - Li Monolithic Power Systems (MPS) - U1 MP2617H with integrated Power Path Management function : Suggested components for battery charging and power path management application circuit 16 Table 19 Table / 27 Figure , and in particular , for the parts recommended to be section See the ☞ 2.2.1.10 provided if the application device integrates an internal antenna. - in 16029218 - R11 Design - UBX Page 50 of 116

51 SARA - System Integration Manual - R4/N4 series R412M - Guidelines for particular VCC supply circuit design for SARA 2.2.1.8 SARA VCC pins (see 3 rate supply inputs over the ): R412M modules have sepa - Figure pins #52 and #53: supply input for the internal RF Power Amplifier, demanding most of the  VCC total current drawn of the module when RF transmission is enabled during a call VCC ceiver Band and Trans - pin #51: supply input for the internal Power Management Unit, Base  parts, demanding minor current Generally, all the connected to the same external power supply circuit, pins are intended to be VCC but separate supply sources can be implemented fo r specific (e.g. battery - powered) applications. The voltage at the VCC pins #52 and #53 can drop to a value lower than the one at the VCC pin #51, on and functional illustrates a possible application keeping the module still switched 25 Figure . - circuit. D1 L1 SARA R412M - up - Step Regulator SW 51 VIN VCC R1 C8 SHDNn FB C7 C6 R2 GND U1 - Ion/Li - Pol Li 52 VCC Battery 53 VCC + C1 C3 C2 C5 C4 GND : VCC circuit example with separate supply for SARA 25 - R412M modules Figure - Part Number Manufacturer iption Descr Reference C1 Kemet – T520B107M006ATE015 100  F Capacitor Tantalum B_SIZE 20% 6.3V 15m μ 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata C2 - 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 C3 Murata C4 56 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E560JA01 - Murata Murata C5 15 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1E150JA01 - - GRM188R60J106ME47 F Capacitor Ceramic X5R 0603 20% 6.3 V μ 10 C6 Murata 22 μ F Capacitor Ceramic X5R 1210 10% 25 V C7 GRM32ER61E226KE15 - Murata Murata - GRM1555C1E100JA01 10 pF Capacitor Ceramic C0G 0402 5% 25 V C8 Vishay General Semiconductor - SS14 Schottky Diode 40 V 1 A D1 L1 SRN3015 100M - Bourns Inc. -  H Inductor 20% 1 A 276 m μ 10 R1 Generic manufacturer Resistor 0402 5% 0.063 W 1 M  Generic manufacturer R2  412 k Resistor 0402 5% 0.063 W - AP3015 up Regulator 350 mA - Step U1 Diodes Incorporated Table R412M modules - : Examples of components for the VCC circuit with separate 17 supply for SARA Figure , for the parts recommended to be 19 Table / 27 ☞ , and in particular 2.2.1.10 section See the a. provided if the application device integrates an internal antenn - in 16029218 - R11 Design - UBX Page 51 of 116

52 R4/N4 series SARA System Integration Manual - - 2.2.1.9 Guidelines for removing VCC supply VCC Removing the R4/N4 - SARA power can be useful to minimize the current consumption when the modules are switched off or when the modules are in deep sleep Power Saving Mode. series In applications in which the module is paired to a host application processor equipped with a RTC, the volatile memory, module can execute standard PSM procedures, store NAS protocol context in non - and rely on the host application processor to run its RTC and to trigger wake - up upon need. The application processor can disconnect the VCC supply source from the module and zero out the module’s PSM current. - leakage load switch or p - supply source channel can be removed using an appropriate low The VCC that the external switch , given 26 Figure MOSFET controlled by the application processor as shown in has provide:  Very low leakage current (for example, less than 1 μ A), to minimize the current consumption  Very low R ), to minimize voltage drops series resistance (for example, less than 50 m  DS(ON) SARA R4/N4 series - Adequate maximum Drain current (see the Data Sheet current for module [1]  consumption figures) SARA - R4/N4 U1 51 VCC 52 VCC VCC Supply Source VIN VOUT + 53 VCC CT VBIAS C4 C2 C5 C3 C1 ON GND GPIO Application GPIO 4 V_INT Processor 15 PWR_ON R2 GPIO T1 R1 GND GND : Example of application circuit for VCC supply removal 26 Figure - Part Number Description Reference Manufacturer C1 T520B107M006ATE015 – Kemet 100 μ F Capacitor Tantalum B_SIZE 20% 6.3V 15m  10 C2 Murata nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata C3 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - 68 pF Capacitor Ceramic C0G 0402 5% 50 V C4 Murata - GRM1555C1H680JA01 15 pF Capacitor Ceramic C0G 0402 5% 25 V C5 GRM1555C1E150JA01 - Murata - 0747KL - RC0402JR R1, R3 Yageo Phycomp  Resistor 0402 5% 0.1 W 47 k 0710KL - Yageo Phycomp R2 RC0402JR -  Resistor 0402 5% 0.1 W 10 k Infineon - T1 BC847 NPN BJT Transistor - Low Resistance Load Switch Texas Instruments U1 Ultra - TPS22967 18 : Components for VCC supply removal application circuit Table ☞ SARA supply during - VCC R4/N4 series It is highly recommended to avoid an abrupt removal of the V_INT supply can be removed only after VCC : the normal operations goes low, indicating that the - Power Saving Mode or Power Off Mode. module has entered Sleep - Deep 19 / 27 Figure , for the parts recommended to be Table 2.2.1.10 section See the ☞ , and in particular provided if the application device integrates an internal antenna. - in 16029218 - R11 Design - UBX Page 52 of 116

53 SARA System Integration Manual - R4/N4 series - Additional guidelines for VCC supply circuit design 2.2.1.10 power source. The series resistance of the supply lines To reduce voltage drops, use a low impedance VCC (connected to the modules’ and GND pins) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize losses. connection. Three pins are allocated to connection . Several pins are designated for GND VCC supply It is recommended to correctly connect all of them to supply the module minimizing series resistance. To reduce voltage ripple and noise, improving RF perfor mance especially if the application device VCC integrates an internal antenna, place the following bypass capacitors near the pins: Resonant Frequency in the 800/900 MHz range (e.g. Murata - 68 pF capacitor with Self  cellular frequency bands GRM1555C1H680J ), to filter EMI in the low  15 pF capacitor with Self - Resonant Frequency in the 1800/1900 MHz range (as Murata GRM1555C1H150J ), to filter EMI in the high cellular frequency bands rom clocks and data 10 nF capacitor (e.g. Murata GRM155R71C103K), to filter digital logic noise f   100 nF capacitor (e.g. Murata GRM155R61C104K), to filter digital logic noise from clocks and data at the An additional capacitor is recommended to avoid undershoot and overshoot at the start and : transmission end of RF F low ESR capacitor (e.g Kemet T520B107M006ATE015), for SARA μ 100  - R412M supporting 2G  modules R4/N4 series - that do not support 2G the other F capacitor (or greater), for μ 10 SARA noise filtering , in particular if the RF series An additional ditional ferrite bead is recommended for ad application device integrates an internal antenna :  Ferrite bead specifically designed for EMI suppression in GHz band (e.g. Murata BLM18EG221SN1), pins of the module, VCC placed as close as possible to the implementing the circuit described in to filter out EMI in all the cellular bands Figure 27 , C5 Capacitor with SARA - R4/N4 SRF ~900 MHz 3V8 Ferrite Bead Capacitor with 51 VCC for GHz noise SRF ~1900 MHz FB1 GND plane 52 VCC 53 VCC SARA + C4 C1 C2 C3 FB1 C5 C1 C2 C3 C4 VCC line GND Figure 27 : Suggested design to reduce ripple / noise on VCC, highly recommended when using an integrated antenna Reference Description Part Number - Manufacturer Murata C1 68 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H680JA01 - Murata - GRM1555C1H150JA01 15 pF Capacitor Ceramic C0G 0402 5% 50 V C2 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 - Murata C3 C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata C5 Kemet T520B107M006ATE015 – F Capacitor Tantalum B_SIZE 20%  6.3V 15m 100 μ 10 μ F Capacitor Ceramic X5R 0603 20% 6.3 V Murata GRM188R60J106ME47 - Chip Ferrite Bead EMI Filter for GHz Band Noise - FB1 Murata BLM18EG221SN1  at 100 MHz, 260 220  at 1 GHz, 2000 mA : Suggested components to reduce ripple / noise on VCC 19 Table ☞ The necessity of each part depends on the specific design, but it is recommended to provide all 19 Table / 27 Figure described in parts the if the application device integrates an internal antenna. - in 16029218 - R11 Design - UBX Page 53 of 116

54 SARA - System Integration Manual - R4/N4 series - supply pins is 1 kV (HBM according to JESD22 VCC ESD sensitivity rating of the A114). Higher ☞ line is externally accessible on the application board, e.g. if protection level can be required if the accessible battery connector is directly connected to the supply pins. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to access ible point. 2.2.1.11 Guidelines for VCC supply layout design pins with DC supply source is required for correct RF VCC Good connection of the module performance. Guidelines are summarized in the following list: pins must be connected to the DC source VCC All the available  VCC  connection must be as wide as possible and as short as possible  Any series component with Equivalent Series Resistance (ESR) greater than few milliohms must be avoided VCC  area separated from RF lines / parts, sensitive connection must be routed through a PCB analog signals and sensitive functional units: it is good practice to interpose at least one layer of PCB ground between the VCC track and other signal routing  connection must be routed as far as possibl e from the antenna, in particular if embedded in VCC the application device 28 : see Figure  Coupling between avoided. VCC and digital lines, especially USB, must be 2.2.1.10  The tank bypass capacitor with low ESR for current spikes smoothing described in section VCC should be placed close to the DC converter, place - pins. If the main DC source is a switching DC ider track length. Otherwise cons the large capacitor close to the DC - DC output and minimize VCC - using separate capacitors for DC DC converter and module tank capacitor and Table 19  should be placed as The bypass capacitors in the pF range described in Figure 27 VCC line narrows close to the module input pins, close as possible to the VCC where the pins, he band centered on the Self - Resonant Frequency of the pF improving the RF noise rejection in t capacitors. This is highly recommended if the application device integrates an internal antenna input provide the supply to RF Power Amplifiers, voltage ripple at high frequency may Since VCC  in unwanted spurious modulation of transmitter RF signal. This is more likely to happen with result DC converters, in which case it is better to select the highest operating frequency - switching DC C filter before connecting to - RA SA the - for the switcher and add a large L modules in R4/N4 series the worst case -  DC converter circuit, or at least the use of shielded inductors for the Shielding of switching DC plies may potentially switching DC - DC converter, may be considered since all switching power sup - frequency high - generate interfering signals as a result of high power switching. is protected by transient voltage suppressor to ensure that the voltage maximum ratings VCC If  th from the DC source toward the are not exceeded, place the protecting device along the pa module, preferably closer to the DC source (otherwise protection function may be compromised) Antenna Antenna Antenna ANT VCC VCC ANT SARA SARA ANT NOT OK SARA VCC OK NOT OK embedded antenna VCC line routing guideline for designs integrating an : 28 Figure - in 16029218 - R11 Design - UBX Page 54 of 116

55 - SARA System Integration Manual - R4/N4 series 2.2.1.12 Guidelines for grounding layout design GND Good connection of the module pins with application board solid ground layer is required for correct RF performance. It significantly reduces EMC issues and provides a thermal heat sink for the mo dule. pin with application board solid GND layer. It is strongly recommended that GND Connect each  each GND pad surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The C source through GND as ground current: provide supply current flows back to main D  VCC adequate return path with suitable uninterrupted ground plane to main DC source  It is recommended to implement one layer of the application board as ground plane as wide as possible s a multilayer PCB, then all the board layers should be filled with GND plane  If the application board i as much as possible and each GND area should be connected together with complete via stack ground down to the main ground layer of the board. Use as many vias as possible to connect the planes Provide a dense line of vias at the edges of each ground area, in particular along RF and high speed  lines If the whole application device is composed by more than one PCB, then it is required to provide a  tween the GND areas of all the different PCBs good and solid ground connection be  pads also ensures thermal heat sink. This is critical during connection, GND Good grounding of when the real network commands the module to transmit at maximum power: correct grounding helps prevent module over heating. Generic digital interfaces supply output (V_INT) 2.2.2 Guidelines for V_INT circuit design 2.2.2.1 provide modules R4/N4 series - SARA generic digital interfaces 1.8 V supply output, which V_INT the can be mainly used to: Indicate when the module is switched on and it is not in the deep sleep power saving mode (as  described in sections 1.6.1 , 1.6.2 )  for more details) Pull - up SIM detection signal (see section 2.5  Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. 2.6.1 ) see ltage regulators providing supply for external devices  Enable external vo supply (see Do not apply loads which might exceed the maximum available current from V_INT ☞ ) as this can cause malfunctions in internal circuitry. [1] Data Sheet R4/N4 series - SARA ☞ V_INT can only be used as an output: do not connect any external supply source on V_INT . ESD sensitivity rating of the - according to JESD22 HBM A114). Higher ☞ n is 1 kV ( V_INT supply pi protection level could be required if the line is externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG) close to accessible point. pin to sense the end of the internal switch - the off sequence V_INT ☞ It is recommended to monitor of modules: VCC supply can be removed only after V_INT goes low. R4/N4 series - SARA pin on the ap V_INT It is recommended to provide direct access to the ☞ plication board by means of V_INT an accessible test point directly connected to the pin. - in 16029218 - R11 Design - UBX Page 55 of 116

56 SARA - System Integration Manual - R4/N4 series 2.3 System functions interfaces 2.3.1 Module power - on (PWR_ON) 2.3.1.1 Guidelines for PWR_ON circuit design input is equipp ed with an internal active pull up resistor; an external - PWR_ON R4/N4 series - SARA up resistor is not required and should not be provided. - pull If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device. According to EMC/ESD re quirements of the application, an additional ESD and Table 20 . Figure 29 protection should be provided close to the accessible point, as described in ESD sensitivity rating of the PWR_ON pin is 1 kV (Human Body Model accor ding to JESD22 - A114). ☞ Higher protection level can be required if the line is externally accessible on the application board, pin, and it can be achieved by PWR_ON e.g. if an accessible push button is directly connected to PCOS CA05P4S14THSG varistor) close to the accessible point. mounting an ESD protection (e.g. E from input PWR_ON An open drain or open collector output is suitable to drive the an application . 29 Figure processor, as described in ☞ input pin should not be driven high by an external device, as it may cause start up issues. PWR_ON Application R4/N4 SARA - SARA - R4/N4 Processor Open on - Power Drain push button Output TP TP 15 15 PWR_ON PWR_ON ESD Figure : PWR_ON application circuits using a push button and an open drain output of an application processor 29 Remarks Description Reference - ESD CT0402S14AHSG Varistor array for ESD protection EPCOS : Example ESD protection component for the PWR_ON application circuit Table 20 It is recommended to provide direct access to the PWR_ON ☞ pin on the application board by means PWR_ON pin. of an accessible test point directly connected to the 2.3.1.2 Guidelines for PWR_ON layout design The power - on circuit ( PWR_ON ) requires careful layout sinc e it is the sensitive input available to switch on and switch off the SARA - R4/N4 series modules. It is required to ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power on request. - - in 16029218 - R11 Design - UBX Page 56 of 116

57 R4/N4 series SARA - System Integration Manu al - 2.3.2 Module reset (RESET_N) Guidelines for RESET_N circuit design 2.3.2.1 R4/N4 series - SARA or is not up resist - up; an external pull - is equipped with an internal pull RESET_N required. input to a push button, the pin will be externally accessible on the RESET_N connecting the If application device. According to EMC/ESD requirements of the application, an additional ESD protection device (e.g. the EPCOS CA05P4S14THSG v aristor) should be provided close to accessible 21 and Table Figure . 30 point on the line connected to this pin, as described in A114). Higher RESET_N pin is 1 kV (HBM according to JESD22 ESD sensitivity rating of the - ☞ if protection level can be required if the line is externally accessible on the application board, e.g. pin, and it can be achieved by RESET_N an accessible push button is directly connected to the mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to accessible point. An open drain output or open collector output is suitable to drive th an from input RESET_N e . 30 Figure application processor, as described in input pin should not be driven high by an external device, as it ma RESET_N ☞ y cause start up issues. Application - SARA R4/N4 SARA - R4/N4 Processor Open - on Power Drain push button Output TP TP 18 18 RESET_N RESET_N ESD Figure 30 : RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks EPCOS ESD protection CT0402S14AHSG Varistor for ESD - 21 : Example of ESD protection component for the RESET_N application circuits Table ☞ If the external reset function is not required by the customer application, the RESET_N input pin can be left uncon nected to external components, but it is recommended providing direct access RESET_N on the application board by means of an accessible test point directly connected to the pin. 2.3.2.2 Guidelines for RESET_N layout design The require careful layout due to the pin function: ensure that the voltage level is well RESET_N circuit defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious reset request. It is recommended to keep the connect pin as RESET_N ion line to short as possible. - in 16029218 - R11 Design - UBX Page 57 of 116

58 - SARA - System Integration Manual R4/N4 series Antenna interface 2.4 R4/N4 series - SARA pin ANT modules provide an RF interface for connecting the external antenna: the n and reception. represents the RF input/output for RF signals transmissio The pin has a nominal characteristic impedance of 50 ANT and must be connected to the physical  antenna through a 50  transmission line to allow clean transmission / reception of RF signals. Antenna RF interface (ANT) 2.4.1 for antenna selection and design 2.4.1.1 General guidelines The antenna is the most critical component to be evaluated. Designers must take care of the antenna from all perspective at the very start of the design phase when the physical dimensions of the application board are under analysis/decision, since the RF compliance of the device integrating modules with all the applicable required certification schemes depends on R4/N4 series SARA - antenna’s radiating performance. ically available as: Cellular antennas are typ  External antennas (e.g. linear monopole): o External antennas basically do not imply physical restriction to the design of the PCB where R4/N4 series - SARA the module is mounted. o ce mainly depends on the antennas. It is required to select antennas The radiation performan with optimal radiating performance in the operating bands. RF cables should be carefully selected to have minimum insertion losses. Additional insertion o loss will be introduced by low qua lity or long cable. Large insertion loss reduces both transmit and receive radiation performance. to - RF connector provides a clean PCB  A high quality 50 o cable transition. It is - RF - provided by the recommended to strictly follow the layout and cable termination guidelines connector manufacturer.  Integrated antennas (e.g. PCB antennas such as patches or ceramic SMT elements): Internal integrated antennas imply physical restriction to the design of the PCB: Integrated o antenna excites RF currents on its counte rpoise, typically the PCB ground plane of the device that becomes part of the antenna: its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that should be of the wavelength of the minimum frequency that needs to be radiated, similar to the quarter given that the orientation of the ground plane relative to the antenna element must be As numerical example, the physical restriction to the PCB design can be considered. following: considered as  Wavelength = 40 cm  Minimum GND plane size = 10 cm Frequency = 750 MHz o Radiation performance depends on the whole PCB and antenna system design, including product mechanical design and usage. Antennas should be selected with optimal radiatin g performance in the operating bands according to the mechanical specifications of the PCB and the whole product. It is recommended to select a custom antenna designed by an antennas’ manufacturer if the o . less than 6.5 cm long and 4 cm wide). The required ground plane dimensions are very small (e.g antenna design process should begin at the start of the whole product design process o It is highly recommended to strictly follow the detailed and specific guidelines provided by the correct installation and deployment of the antenna system, antenna manufacturer regarding including PCB layout and matching circuitry o Further to the custom PCB and product restrictions, antennas may require tuning to obtain e required certification schemes. the required performance for compliance with all the applicabl - It is recommended to consult the antenna manufacturer for the design in guidelines for antenna matching relative to the custom application - in 16029218 - R11 Design - UBX Page 58 of 116

59 R4/N4 series SARA - System Integration Manual - ould be observed: In both of cases, selecting external or internal antennas, these recommendations sh Select an antenna providing optimal return loss (or VSWR) figure over all the operating  frequencies. Select an antenna providing optimal efficiency figure over all the operating frequencies.   gure (i.e. combined antenna directivity and Select an antenna providing appropriate gain fi not exceed the regulatory efficiency figure) so that the electromagnetic field radiation intensity do (e.g. by FCC in the United States, as reported in the section limits specified in some countries ). 4.2.2 2.4.1.2 Guidelines for antenna RF interface design Guidelines for ANT pin RF connection design pad and the application board PCB must be provided, ANT A clean transition between the ANT in guidelines for the layout of the application PCB close to the - implementing the following design pad: lines On a multilayer board, the whole layer stack below the RF connection should be free of digital  ANT out (i.e. clearance, a void area) around the - Increase GND keep  pad, on the top layer of the m on the μ m up to adjacent pads metal definition and up to 400 μ application PCB, to at least 250 area below the module, to reduce parasitic capacitance to ground, as described in the left picture in 31 Figure ANT out (i.e. clearance, a void area) on the buried metal layer below the - he  Add GND keep pad if t layer to buried layer dielectric thickness is below 200 μ top - m, to reduce parasitic capacitance to Figure 31 ground, as described in the right picture in GND clearance GND clearance to top layer on buried layer very close on top layer below ANT pad around ANT pad Min. 250 μ m GND ANT Min. 400 μ m Figure 31 out area on top layer around ANT pad and on very close buried layer below ANT pad - : GND keep Guidelines for RF transmission line design pad up to the related antenna connector or ANT Any RF transmission line, such as the ones from the up to the related internal antenna pad, must be designed so that the characteristic impedance is as close as possible to 50  . esigned as a micro strip (consists of a conducting strip separated from RF transmission lines can be d a ground plane by a dielectric material) or a strip line (consists of a flat strip of metal which is cro strip, sandwiched between two parallel ground planes within a dielectric material). The mi implemented as a coplanar waveguide, is the most common configuration for printed circuit board. provide two examples of suitable 50  coplanar waveguide designs. The first 33 32 Figure Figure and - example of RF transmission line can be implemented in case of 4 - cribed, up herein des layer PCB stack layer PCB stack up and the second example of RF transmission line can be implemented in case of 2 - - herein described. - in 16029218 - R11 Design - UBX Page 59 of 116

60 SARA - System Integration Manual - R4/N4 series μ 500 m μ 500 m μ 380 m 35 μ m L1 Copper - FR 4 dielectric m μ 270 μ m L2 Copper 35 - FR 4 dielectric 760 μ m 35 μ m L3 Copper m μ FR 4 dielectric 270 - 35 μ m L4 Copper : Example of 50 - layer board layup Figure 32  coplanar waveguide transmission line design for t he described 4 μ m 400 μ m 400 μ m 1200 μ L1 Copper 35 m m μ - 4 dielectric FR 1510 m μ L2 Copper 35 Figure layer board layup - coplanar waveguide transmission line design for the described 2  : Example of 50 33 If the two examples do not match the application PCB - up, then the 50  stack characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation, or using freeware tools like Avago / Broadcom ) AppCAD ( https://www.broadcom.com/appcad taking care of the approximation formulas used by the tools for the impedance computation. To achieve a 50  characteristic impedance, the width of the transmission line must be chosen depending on: and 32 m in the example of μ ) 33 Figure  the thickness of the transmission line itself (e.g. 35 Figure the thickness of the dielectric material between the top layer (where the transmission line is  , 1510 32 Figure m in μ routed) and the inner closer layer implementing the ground plane (e.g. 270 m μ in Figure 33 )  4 dielectric - the dielectric constant of the dielectric material (e.g. dielectric constant of the FR Figure ) Figure and material in 32 33 the gap from the transmission line to the adjacent ground plane on the same layer of the  Figure m in ) μ ion line (e.g. 500 transmiss 33 Figure m in μ , 400 32 If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5 times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50  calculation. Additionally to the 50 nce, the following guidelines are recommended for transmission lines impeda  design:  Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB, - in 16029218 - R11 Design - UBX Page 60 of 116

61 - SARA - System Integration Manual N4 series R4/ area) on buried metal layers below any pad of component out (i.e. clearance, a void - Add GND keep  layer to buried layer dielectric thickness is below - present on the RF transmission lines, if top 200 m, to reduce parasitic capacitance to ground, μ  The transmission lines width and spacing to GND must be uniform and routed as smoothly as possible: avoid abrupt changes of width and spacing to GND, Add GND stitching vias around transmission lines, as described in , 34  Figure  Ensure solid metal connection of the adjacent metal layer on the PCB stack - up to main ground , 34 Figure layer, providing enough vias on the adjacent metal layer, as described in  Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive circuit (as USB), ission lines,  Avoid stubs on the transm Avoid signal routing in parallel to transmission lines or crossing the transmission lines on buried  metal layer,  Do not route microstrip lines below discrete component or other mechanics placed on top layer Figure it design are illustrated in Two examples of a suitable RF circu , where the antenna detection 34 pplication, follow the circuit is not implemented (if the antenna detection function is required by the a 2.4.2 guidelines for circuit and layout implementation detailed in section ):  pin is directly connected to an SMA connector by ANT In the first example shown on the left, the  means of a suitable 50 transmission line, designed with the appropriate layout. ANT  pin is connected to an SMA connector by In the second example shown on the right, the means of a suitable 50  transmiss ion line, designed with the appropriate layout, with an additional high pass filter to improve the ESD immunity at the antenna port. (The filter consists of a suitable series capacitor and shunt inductor, for example the Murata GRM1555C1H150JA01 Resonant Frequency - citor and the Murata LQG15HN39NJ02 39 nH inductor with Self pF capa 15 GHz.). ~1 SARA module SARA module High - pass filter to improve SMA SMA ESD immunity connector connector : Example of circuit and layout for antenna RF circuits on the application board 34 Figure Guidelines for RF termination design as well as the RF transmission  The RF termination must provide a characteristic impedance of 50 line up to the RF termination, to match the characteristic impedance of the ANT port. However, real antennas do not have a perfect 50 d on all the supported frequency bands. So to  loa reduce as much as possible any performance degradation due to antenna mismatching, the RF termination must provide optimal return loss (or VSWR) figures over all the operating frequencies, as . 7 Table summarized in - in 16029218 - R11 Design - UBX Page 61 of 116

62 SARA - System Integration Manual - R4/N4 series If an external antenna is used, the antenna connector represents the RF termination on the PCB: - RF - to - B connector providing a clean PC  Use suitable a 50  cable transition. Strictly follow the connector manufacturer’s recommended layout, for example:  Through Hole connectors require a GND keep o out (i.e. clearance, a void area) on all - SMA Pin - - the layers around the central pin up to the annular pads of the four GND posts, as shown in 34 Figure U.FL surface mounted connectors require no conductive traces (i.e. clearance, a void area) in o the area below the connector between the GND land pads. Cut out the GND layer under the RF connector and close to any b  uried vias, to remove stray capacitance and thus keep the RF line at 50  , e.g. the active pad of UFL connector needs to have a GND keep out (i.e. clearance, a void area) at least on the first inner layer to reduce parasitic - capacitance to ground. If an in tegrated antenna is used, the integrated antenna represents the RF terminations. The following guidelines should be followed: Use an antenna designed by an antenna manufacturer providing the best possible return loss (or  VSWR).  Provide a ground plane large enough according to the relative integrated antenna requirements. The ground plane of the application PCB can be reduced down to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that needs to be radiated. As numeri cal example,  Frequency = 750 MHz Minimum GND plane size = 10 cm Wavelength = 40 cm  It is highly recommended to strictly follow the detailed and specific guidelines provided by the  the antenna system, antenna manufacturer regarding correct installation and deployment of including the PCB layout and matching circuitry.  Further to the custom PCB and product restrictions, the antenna may require a tuning to comply with all the applicable required certification schemes. It is recommended to consult the ant enna in guidelines for the antenna matching relative to the custom - manufacturer for the design application. Additionally, these recommendations regarding the antenna system placement must be followed: Do not place the antenna within a closed metal case.   Do not place the antenna in close vicinity to the end user since the emitted radiation in human tissue is restricted by regulatory requirements. as Place the antenna  ), 28 Figure (refer to and related parts line VCC supply from as possible far high speed digital lines (as USB) and from from any possible noise source . C Place the antenna far from sensitive analog systems or employ countermeasures to reduce EM  issues. or EMI  located RF systems since the LTE transmitted power may Be aware of interaction between co - interact or disturb the performance of companion systems. - in 16029218 - R11 Design - UBX Page 62 of 116

63 SARA - System Integration Manual - R4/N4 series Examples of antennas - board surface - lists some examples of possible internal on 22 Table mount antennas. Description Product Name Part Number Manufacturer Taoglas PA.710.A Warrior GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 40.0 x 6.0 x 5.0 mm Taoglas PCS.06.A Havok GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2500..2690 MHz 42.0 x 10.0 x 3.0 mm GSM / WCDMA / LTE SMD Antenna MCS6.A Taoglas 698..960 MHz, 1710..2690 MHz 42.0 x 10.0 x 3.0 mm Antenova SR4L002 Lucida GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2490..2690 MHz 35.0 x 8.5 x 3.2 mm GSM / WCDMA / LTE SMD Antenna P822601 Ethertronics 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE SMD Antenna P822602 Ethertronics 698..960 MHz, 1710..2170 MHz, 2490..2700 MHz 50.0 x 8.0 x 3.2 mm GSM / WCDMA / LTE Vertical Mount Antenna 1002436 Ethertronics 698..960 MHz, 1710..2700 MHz 50.6 x 19.6 x 1.6 mm GSM / WCDMA / LTE SMD Antenna Domino W3796 Pulse 698..960 MHz, 1427..1661 MHz, 1695..2200 MHz, 2300..2700 MHz 42.0 x 10.0 x 3.0 mm TE Connectivity 1 - 2118310 GSM / WCDMA / LTE Vertical Mount Antenna 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 74.0 x 10.6 x 1.6 mm Molex 1462000001 GSM / WCDMA / LTE SMD Antenna 698..960 MHz, 1700..2700 MHz 40.0 x 5.0 x 5.0 mm Cirocomm DPAN0S07 GSM / WCDMA / LTE SMD Antenn a 698..960 MHz, 1710..2170 MHz, 2500..2700 MHz 37.0 x 5.0 x 5.0 mm Table : Examples of internal surface - mount antennas 22 - in 16029218 - R11 Design - UBX Page 63 of 116

64 SARA System Integration Manual - R4/N4 series - type antennas with cable and board PCB - lists some examples of possible internal off 23 Table - connector. Description Part Number Manufacturer Product Name Taoglas FXUB63.07.0150C GSM / WCDMA / LTE PC B Antenna with cable and U.FL 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz 96.0 x 21.0 mm Taoglas GSM / WCDMA / LTE PCB Antenna with cable and U.FL FXUB66.07.0150C Maximus 698..960 MHz, 1390..1435 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz, 3400..3600 MHz, 4800..6000 MHz 120.2 x 50.4 mm SRFL029 Antenova GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL Moseni 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm SRFL026 Antenova GSM Mitis / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 689..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 110.0 x 20.0 mm Ethertronics 1002289 GSM / WCDMA / LTE Antenna on flexible PCB with cable and U.FL 698..960 MHz, 1710..2700 MHz x 75.0 mm 140.0 EAD GSM / WCDMA / LTE PCB Antenna with cable and U.FL SQ7 FSQS35241 10 - UF - 690..960 MHz, 1710..2170 MHz, 2500..2700 MHz 110.0 x 21.0 mm 23 Table : Examples of internal antennas with cable and connector 24 lists some examples of possible external antennas. Table Part Number Manufacturer Description Product Name mount antenna with cable and SMA(M) Phoenix GSA.8827.A.101111 GSM / WCDMA / LTE adhesive - Taoglas 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2490..2690 MHz 105 x 30 x 7.7 mm GSM / WCDMA / LTE swivel dipole antenna with SMA(M) Taoglas TG.30.8112 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2700 MHz 148.6 x 49 x 10 mm GSM / WCDMA / LTE MIMO 2in1 adhesive - mount combination antenna Genesis Taoglas MA241.BI.001 waterproof IP67 rated with cable and SMA(M) 698..960 MHz, 1710..2170 MHz, 2400..2700 MHz 205.8 x 58 x 12.4 mm - TRA6927M3PW - GSM / WCDMA / LTE screw type(F) Laird Tech. - mount antenna with N 001 698..960 MHz, 1710..2170 MHz, 2300..2700 MHz 83.8 x Ø 36.5 mm mount antenna with cable and N GSM / WCDMA / LTE ceiling - CMS69273 type(F) Laird Tech. - 698..960 MHz, 1575.42 MHz, 1710..2700 MHz 86 x Ø 199 mm type(M) FNM Laird Tech. GSM / WCDMA / LTE pole OC69271 mount antenna with N - - - 698..960 MHz, 1710..2690 MHz 248 x Ø 24.5 mm Pulse GSM / WCDMA / LTE clip - mount MIMO antenna with cables and WA700/2700SMA SMA(M) ectronics El 698..960 MHz,1710..2700 MHz 149 x 127 x 5.1 mm 24 Table : Examples of external antennas UBX - 16 029218 - R11 Design - in Page 64 of 116

65 R4/N4 series SARA System Integration Manual - - Antenna detection interface (ANT_DET) 2.4.2 2.4.2.1 for ANT_DET circuit design Guidelines Table schematic / components for the antenna detection describe the recommended 25 and Figure 35 circuit that must be provided on the application board and for the diagnostic circuit that must be tenna’s assembly to achieve antenna detection functionality. provided on the an Diagnostic Radiating Element Circuit R4/N4 SARA - C3 C2 C4 ohm = 50 Z 0 = 50 = 50 Ω Z Z Ω 0 0 56 ANT Antenna Cable L2 J1 L3 R1 L1 62 ANT_DET R2 D1 C1 GND Application Board Antenna Assembly and diagnostic circuit on antenna assembly PCB : Suggested schematic for antenna detection circuit on application 35 Figure Reference Descri ption Part Number - Manufacturer C1 Murata - 27 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H270J - Murata C2 33 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H330J D1 - PESD0402 Tyco Electronics - 140 Very Low Capacitance ESD Protection LQG15HS68NJ02 L1 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) Murata - R1 KOA Speer - RK73H1ETTP1002F 10 k Resistor 0402 1% 0.063 W  SMA6251A1 J1 3GT50G - 50 - Amphenol - SMA Connector 50  Through Hole Jack Murata - GRM1555C1H150J C3 15 pF Capacitor Ceramic C0G 0402 5% 50 V 39 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HN39NJ02 - Murata L2 C4 22 pF Capacitor Ceramic C0G 0402 5% 25 V GRM1555C1H220J - Murata - Murata L3 68 nH Multilayer Inductor 0402 (SRF ~1 GHz) LQG15HS68NJ02 Various Manufacturers R2  Resistor for Diagnostics 15 k and diagnostic circuit on antennas assembly PCB for antenna detection circuit on application parts : Suggested Table 25 The antenna detection circuit and diagnostic circuit suggested in 35 and Table 25 are here Figure explained:  When antenna detection is forced by the +UANTR AT command, the ANT_DET pin generates a DC current measuring the resistance (R2) from the antenna connector (J1) provided on the application board to GND. pin (C2)  ANT DC blocking capacitors are needed at the and at the antenna radiating element (C4) to decouple the DC current generated by the pin. ANT_DET  Choke inductors with a Self Resonance Frequency (SRF) in the range of 1 GHz are needed in series at the ANT_DET pin (L1) and in series at the diagnostic resi stor (L3), to avoid a reduction of the RF performance of the system, improving the RF isolation of the load resistor.  Resistor on the ANT_DET path (R1) is needed for accurate measurements through the +UANTR AT command. It also acts as an ESD protection. ) are needed at the 35 Figure pin as ESD protection. ANT_DET  Additional components (C1 and D1 in ) is provided at the ANT pin as ESD immunity Additional high pass filter (C3 and L2 in Figure 35  improvement pin must be connected to the antenna connector by means of a transmission line with ANT The  .  nal characteristics impedance as close as possible to 50 nomi - in 16029218 - R11 Design - UBX Page 65 of 116

66 - SARA - System Integration Manual R4/N4 series The DC impedance at RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short , 35 Figure to reference GND (e.g. PIFA antenna). For those antennas, without the diagnostic circuit of the measured DC resistance is always at the limits of the measurement range (respectively open or short), and there is no mean to distinguis h between a defect on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna). Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating ll alter the measurement and produce invalid results for antenna detection. element wi to  k ☞ - in diagnostic resistor in the range from 5 It is recommended to use an antenna with a built le RF 30 k  to assure good antenna detection functionality and avoid a reduction of modu performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) in the range of 1 GHz to improve the RF isolation of load resistor. For example: . Using the +UANTR A  Consider an antenna with built - T command, the in DC load resistor of 15 k module reports the resistance value evaluated from the antenna connector provided on the application board to GND:   to 17 k  Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 k  k if a 15 diagnostic res istor is used) indicate that the antenna is correctly connected. circuit  Values close to the measurement range maximum limit (approximately 50 k  ) or an open - AT Commands Man R4/N4 series - SARA range” report (see the “over [2] ) means that that the ual antenna is not connected or the RF cable is broken.  Reported values below the measurement range minimum limit (1 k  ) h ighlights a short to GND at antenna or along the RF cable.  Measurement inside the valid measurement range and outside the expected range may indicate an unclean connection, a damaged antenna or incorrect value of the antenna load resistor for diagnostics.  Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method. If the antenna detection function is not required ☞ by the customer application, the ANT_DET pin can be left not connected and the pin can be directly connected to the antenna connector by ANT . means of a 50  transmission line as described in Figure 34 - in 16029218 - R11 Design - UBX Page 66 of 116

67 SARA - System Integration Manual - R4/N4 series Guidelines for ANT_DET layout design 2.4.2.2 36 describes the recommended layout for the antenna detection circuit to be provided on the Figure application board to achieve antenna detection functionality, implementing the recommended : Figure 35 and Table 25 schematic described in the previous  ANT The  pin must be connected to the antenna connector by means of a 50 transmission line, menting the design guidelines described in section and the recommendations of the imple 2.4.1 SMA connector manufacturer.  pin (C2) must be placed in series to the 50 ANT DC blocking capacitor at  RF line. pin must be connected to the 50  transmission line by means of a sense line. ANT_DET The   ANT_DET Choke inductor in series at the  pin (L1) must be placed so that one pad is on the 50 transmission li pin. ANT_DET ne and the other pad represents the start of the sense line to the line must be placed as ESD protection. ANT_DET The additional components (R1, C1 and D1) on the   The additional high pass filter (C3 and L2) on the ANT line are placed as ESD immunity improvement SARA module R1 D1 C1 C2 L1 L2 C3 J1 36 Figure : Suggested layout for antenna detection circuit on application board - in 16029218 - R11 Design - UBX Page 67 of 116

68 - SARA - System Integration Manual R4/N4 serie s 2.5 SIM interface 2.5.1 Guidelines for SIM circuit design 2.5.1.1 Guidelines for SIM cards, S IM connectors and SIM chips selection The ISO/IEC 7816, the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical, electrical and functional characteristics of Universal Integrated Circuit Cards (UICC), which contains the Subscriber Id entification Module (SIM) integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the LTE network. Removable UICC / SIM card contacts mapping is defined by ISO/IEC 7816 and ETSI TS 102 221 as follows : It must be connected to  VSIM  Contact C1 = VCC (Supply)   Contact C2 = RST (Reset) It must be connected to SIM_RST  Contact C3 = CLK (Clock)  It must be connected to SIM_CLK  Contact C4 = AUX1 (Auxiliary contact)  It must be left not connected It must be connected to  Contact C5 = GND (Ground)  GND  It can be left not connected  Contact C6 = VPP (Programming supply)  SIM_IO It must be connected to  Contact C7 = I/O (Data input/output) It must be left not connected  Contact C8 = AUX2 (Auxiliary contact)  A removable SIM card can have 6 contacts (C1, C2, C3, C5, C6, C7) or 8 contacts, also including the auxiliary contacts C4 and C8. Only 6 contacts are required and must be connected t o the module SIM interface. Removable SIM cards are suitable for applications requiring a change of SIM card during the product lifetime. A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins relative to the normally - open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided. Select a SIM connector providing 6+2 or 8+2 positions if the optional SIM dete ction feature is required by the custom application, otherwise a connector without integrated mechanical presence switch can be selected. Solderable UICC / SIM chip contact mapping (M2M UICC Form Factor) is defined by ETSI TS 102 671 as:  VSIM It must be connected to Contact C1 = VCC (Supply)  Case Pin 8 = UICC SIM_RST It must be connected to  Case Pin 7 = UICC Contact C2 = RST (Reset)  SIM_CLK  Case Pin 6 = UICC Contact C3 = CLK (Clock)  It must be connected to It must be left not connected  X1 (Aux.contact) Case Pin 5 = UICC Contact C4 = AU  It must be connected to GND  Case Pin 1 = UICC Contact C5 = GND (Ground)   Case Pin 2 = UICC Contact C6 = VPP (Progr. supply)  It can be left not connected  It must be connected to Case Pin 3 = UICC Contact C7 = I/O (Data I/O)  SIM_IO It must be left not connected  Case Pin 4 = UICC Contact C8 = AUX2 (Aux. contact)  A solderable SIM chip has 8 contacts and can also include the auxiliary contacts C4 and C8 for other uses, but only 6 contacts are required and must be connected to the module SIM card interface as described above. Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed. - in 16029218 - R11 Design - UBX Page 68 of 116

69 SARA System Integration Manual - R4/N4 series - 2.5.1.2 Guidelines for single SIM card connection without detection A removable SIM card placed in a SIM card holder must be connected to the SIM card interface of modules as described in R4/N4 series - , where the optional SIM detection feature is Figure SARA 37 not implemented. Follow these guidelines to connect the module to a SIM connector without SIM presence detection: pin of the module. VSIM SIM contacts C1 (VCC) to the Connect the UICC /  pin of the module.  Connect the UICC / SIM contact C7 (I/O) to the SIM_IO  SIM_CLK Connect the UICC / SIM contact C3 (CLK) to the pin of the module.  pin of the module. SIM_RST Connect the UICC / SIM contact C2 (RST) to the  Connect the UICC / SIM contact C5 (GND) to ground. Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) on SIM supply line, close to the  relative pad of the SIM connector, to prevent digital noise. f about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM Provide a bypass capacitor o  line, very close to each related pad of the SIM connector, to prevent RF coupling especially in case the RF antenna is placed closer than 10 30 cm from the SIM card holder. -  Provide a very lo w capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402 - 140) on each externally accessible SIM line, close to each relative pad of the SIM connector. ESD sensitivity rating of the SIM interface pins is 1 kV (HBM). So that, according to EMC/ ESD requirements of the custom application, higher protection level can be required if the lines are externally accessible on the application device. Limit capacitance and series resistance on each SIM signal to match the SIM requirements (18.7  aximum allowed rise time on clock ns is the m s is the maximum allowed rise time on data μ line, 1.0 and reset lines). SIM CARD R4/N4 SARA - HOLDER VPP (C6) C C C C VCC (C1) 41 VSIM 7 6 5 8 IO (C7) 39 SIM_IO C C C C 2 3 4 1 38 CLK (C3) SIM_CLK 40 RST (C2) SIM_RST SIM Card Bottom View GND (C5) (contacts side) C4 C5 C3 C2 C1 D1 D2 D4 D3 J1 detection not implemented Figure 37 : Application circuits for the connection to a single removable SIM card, with SIM Part Number Reference Description Manufacturer - Murata - GRM1555C1H470JA01 47 pF Capacitor Ceramic C0G 0402 5% 50 V C1, C2, C3, C4 - GRM155R71C104KA01 100 nF Capacitor Ceramic X7R 0402 10% 16 V C5 Murata - Low Capacitance ESD Protection Very D1, D2, D3, D4 - 140 Tyco Electronics PESD0402 Various manufacturers, as C707 10M006 136 2 SIM Card Holder, 6 p, without card presence - J1 switch Amphenol 26 : Example of components for the connection to a Table single removable SIM card, with SIM detection not implemented - in 16029218 - R11 Design - UBX Page 69 of 116

70 SARA - System Integration Manual - R4/N4 series Guidelines for single SIM chip connection 2.5.1.3 the A solderable SIM chip (M2M UICC Form Factor) must be connected the SIM card interface of SARA R4/N4 series - les as described in 38 modu . Figure Follow these guidelines to connect the module to a solderable SIM chip without SIM presence detection: VSIM pin of the module. Connect the UICC / SIM contacts C1 (VCC) to the   pin of the module. SIM_IO Connect the UICC / SIM contact C7 (I/O) to the pin of the module. SIM_CLK Connect the UICC / SIM contact C3 (CLK) to the  SIM_RST Connect the UICC / SIM contact C2 (RS  T) to the pin of the module. Connect the UICC / SIM contact C5 (GND) to ground.   Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the relative pad of the SIM chip, to prevent digital noise. Provide a by pass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM  line, to prevent RF coupling especially in case the RF antenna is placed closer than 10 - 30 cm from the SIM lines.  Limit capacitance and series resistance on each SIM signal t o match the SIM requirements ns is the maximum allowed rise time on clock line, 1.0 (18. s is the maximum allowed rise time on μ 7 data and reset lines). SARA - R4/N4 SIM CHIP 2 VPP (C6) 8 41 VCC (C1) VSIM 8 1 C5 C1 3 7 2 C6 C2 IO (C7) 39 SIM_IO 6 C3 C7 3 6 C4 4 C8 5 CLK (C3) 38 SIM_CLK 7 SIM_RST RST (C2) 40 SIM Chip Bottom View 1 GND (C5) (contacts side) C4 C5 C1 C2 C3 U1 connection to a single solderable SIM chip, with SIM detection not implemented Figure 38 : Application circuits for the - Part Number Description Reference Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata C5 Murata - GRM155R71C104KA01 V 100 nF Capacitor Ceramic X7R 0402 10% 16 Various Manufacturers SIM chip (M2M UICC Form Factor) U1 : Example of components for the connection to a single solderable SIM chip, with SIM detection not implemented Table 27 2.5.1.4 Guidelines for single SIM card connection with detection An application circuit for the connection to a single removable SIM card placed in a SIM card holder is 39 Figure described in , where the optional SIM card detection feature is implemented. Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection: VSIM Connect the UICC / SIM contacts C1 (VCC) to the pin of the module.  Connect the UICC / SIM contact C7 (I/O) to the  pin of the module. SIM_IO pin of the module.  Connect the UICC / SIM contact C3 (CLK) to the SIM_CLK  Connect the UICC / SIM contact C2 (RST) to the SIM_RST pin of the module. GND) to ground. Connect the UICC / SIM contact C5 (  - in 16029218 - R11 Design - UBX Page 70 of 116

71 SARA - System Integration Manual - R4/N4 series open mechanical switch integrated in the SIM connector (as the - Connect one pin of the normally  down resistor (e.g. 470 39 input GPIO5 , as  k ) to the SW2 pin in Figure - pin, providing a weak pull R2 in Figure 39 ). n the SIM connector open mechanical switch integrated i - Connect the other pin of the normally  (SW1 pin in 1.8 V supply output by means of a strong pull  k up resistor (e.g. 1 , Figure 39 ) to V_INT - as R1 in ) 39 Figure ),  Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line ( VSIM noise. close to the related pad of the SIM connector, to prevent digital  Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM , SIM_CLK line ( VSIM connector, to ), very close to each related pad of the SIM SIM_RST , SIM_IO , 30 cm from the prevent RF coupling especially in case the RF antenna is placed closer than 10 - SIM card holder.  Provide a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco Electronics 140) on each externally accessib PESD0402 le SIM line, close to each related pad of the SIM - connector. The ESD sensitivity rating of SIM interface pins is 1 kV (HBM according to A114), so that, according to the EMC/ESD requirements of the custom application, higher JESD22 - protection level can be r equired if the lines are externally accessible. Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM  SIM_IO μ and , 1.0 SIM_CLK interface (18.7 ns = maximum rise time on s = maximum rise time on ). SIM_RST SIM CARD HOLDER R4/N4 - SARA TP SW1 4 V_INT R1 42 SW2 GPIO5 R2 VPP (C6) C C C C VCC (C1) 41 VSIM 6 8 7 5 39 IO (C7) SIM_IO C C C C 1 3 4 2 CLK (C3) 38 SIM_CLK RST (C2) 40 SIM_RST SIM Card Bottom View GND (C5) (contacts side) C4 C1 C2 C3 C5 D5 D4 D3 D2 D1 D6 J1 : Application circuit for the connection to a single removable SIM card, with SIM detection implemented 39 Figure Manufacturer Part Number Description Reference - 0402 5% 50 V C1, C2, C3, C4 47 pF Capacitor Ceramic C0G Murata - GRM1555C1H470JA01 100 nF Capacitor Ceramic X7R 0402 10% 16 V C5 Murata - GRM155R71C104KA01 Tyco Electronics - D6 – D1 PESD0402 140 - Very Low Capacitance ESD Protection R1 RC0402JR - 071KL - Yageo Phycomp Resistor 0402 5% 0.1 W  1 k Yageo Phycomp - 07470KL - RC0402JR R2 470 k  Resistor 0402 5% 0.1 W J1 Various Manufacturers, SIM Card Holder CCM03 - 3013LFT R102 - 6 + 2 positions, with card presence switch C&K Components 28 Table : Example of components for the connection to a single removable SIM card, with SIM detection implemented - 16029218 116 of 71 Page - in - Design 1 R1 UBX

72 SARA - System Integration Manual R4/N4 series - Guidelines for SIM layout design 2.5.2 , SIM_CLK , VSIM ( lines card interface The layout of the SIM may be critical if the SIM_RST , SIM_IO modules or in close proximity to the RF SIM card is placed far away from the SARA - R4/N4 series antenna: these two cases should be avoided or at least mitigated as described below. In the first case, the long connection can cause the radi ation of some harmonics of the digital data frequency as any other digital interface. It is recommended to keep the traces short and avoid coupling with RF line or sensitive analog inputs. - self In the second case, the same harmonics can be picked up and create interference that can reduce the sensitivity of LTE receiver channels whose carrier frequency is coincidental with harmonic Figure 37 frequencies. It is strongly recommended to place the RF bypass capacitors suggested in near the SIM connector. In addition, since the SIM card is typically accessed by the end user, it can be subjected to ESD discharges. Add adequate ESD protection as suggested to pro tect module SIM pins near the SIM connector. Limit capacitance and series resistance on each SIM signal to match the SIM specifications. The connections should always be kept as short as possible. Avoid coupling with any sensitive analog circuit, since the SIM signals can cause the radiation of some harmonics of the digital data frequency. in 116 - 16029218 - R11 Design - UBX Page 72 of

73 SARA - System Integration Manual - R4/N4 series Data communication interfaces 2.6 UART interface 2.6.1 2.6.1.1 Guidelines for UART circuit design 12 232 functionality (using the complete V.24 link) Providing the full RS - le signal levels are needed, two different external voltage translators can be used If RS - 232 compatib - for Instruments SN74AVC8T245PW to provide full RS Texas 232 (9 lines) functionality: e.g. using the - the translation from 1.8 V to 3.3 V, and the Maxim MAX3237E for the tran slation from 3.3 V to RS 232 compatible signal level. If a 1.8 V Application Processor (DTE) is used and complete RS 232 functionality is required, then the - Figure 40 . complete 1.8 V UART of the module (DCE) should be connected to a 1.8 V DTE, as in Application Processor R4/N4 - SARA (1.8V DCE) (1.8V DTE) Ω 0 TP 12 TXD TxD 0 Ω TP 13 RXD RxD Ω 0 TP 10 RTS RTS 0 Ω TP 11 CTS CTS 9 DTR DTR 6 DSR DSR 7 RI RI 8 DCD DCD GND GND 40 Figure communication (1.8V DTE) : UART interface application circuit with complete V.24 link in DTE/DCE serial Processor (DTE) is used, then it is recommended to connect the 1.8 V UART of If a 3.0 V Application the module (DCE) by means of appropriate unidirectional voltage translators using the module V_INT 41 . output as 1.8 Figure oltage translators on the module side, as described in V supply for the v R4/N4 SARA Application Processor - (1.8V DCE) (3.0V DTE) Unidirectional 1V8 3V0 Voltage Translator TP 4 VCCB VCCA VCC V_INT C1 C2 DIR1 DIR3 0 Ω TP 12 A1 B1 TxD TXD 0 Ω TP 13 B2 A2 RXD RxD Ω 0 TP 10 A3 B3 RTS RTS 0 Ω TP 11 B4 A4 CTS CTS OE DIR2 DIR4 GND U1 Unidirectional 1V8 3V0 Voltage Translator VCCA VCCB C3 C4 DIR1 9 A1 B1 DTR DTR 6 B2 A2 DSR DSR 7 B3 A3 RI RI B4 A4 8 DCD DCD DIR2 DIR3 OE DIR4 GND GND GND U2 application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) : UART interface 41 Figure Manufacturer Reference Description Part Number - 100 nF Capacitor Ceramic X7R 0402 10% 16 V C1, C2, C3, C4 GRM155R61A104KA01 - Murata 13 - SN74AVC4T774 Unidirectional Voltage U1, U2 Translator Texas Instruments Table 29 : Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE) 12 , but the to must be set low input use the UART Flow control is not supported by ‘ 00 ’ , ‘ 01 ’ and SARA - R410M - 02B product versions RTS DTR ‘x 2 product versions . on ‘ 00 ’ and ‘ 01 ’ versions . The ’ input must be set low to have URCs presented over UART on ‘ 00 ’ , ‘ 01 ’ and 13 3 V DTE partial power down feature so that the ing provid oltage translator V 1.8 V supply V_INT supply can be also ramped up before - 16029218 116 of 73 Page - in - Design R11 UBX

74 R4/N4 series SARA System Integration Manual - - 14 Providing the TXD, RXD, RTS, CTS and DTR lines only and DCD , DSR ality of the If the function lines is not required, or the lines are not available: RI RI DCD point on - lines of the module floating, with a test and DCD , DSR  Leave - If RS 232 compatible signal levels are needed, two different external voltage translators (e.g . Maxim MAX3237E and Texas Instruments SN74AVC4T774) can be used. The Texas Instruments chips provide the translation from 1.8 V to 3.3 V, while the Maxim chip provides the translation from 3.3 V 232 compatible signal level. to RS - Figure describes the circuit that should be implemented as if a 1.8 V Application Processor (DTE) 42 DSR is used, given that the DTE will behave correctly regardless of the put setting. in SARA - R4/N4 Application Processor (1.8V DCE) (1.8V DTE) TP 0 Ω 12 TXD TxD TP 0 Ω 13 RXD RxD TP 0 Ω 10 RTS RTS TP Ω 0 11 CTS CTS 9 DTR DTR 6 DSR DSR 7 RI RI 8 DCD DCD GND GND - : UART interface application circuit with partial V.24 link (6 42 wire) in the DTE/DCE serial communication (1.8 V DTE) Figure is used, then it is If a 3.0 V Application Processor (DTE) V UART recommended to connect the 1.8 interface of the module (DCE) by means of appropriate unidirectional voltage translators using the voltage translators on the module side, as described in module V_INT output as 1.8 V supply for the , given that the DTE will behave correctly regardless of the DSR input setting. 43 Figure SARA - R4/N4 Application Processor (1.8V DCE) (3.0V DTE) Unidirectional 1V8 3V0 Voltage Translator 4 VCCB VCCA VCC V_INT C1 C2 DIR1 DIR3 TP 0 Ω 12 A1 B1 TxD TXD TP Ω 0 13 B2 A2 RxD RXD TP Ω 0 10 B3 A3 RTS RTS TP Ω 0 11 A4 B4 CTS CTS DIR2 OE DIR4 GND U1 Unidirectional 1V8 3V0 Voltage Translator VCCB VCCA C3 C4 DIR2 DIR1 9 DTR DTR B1 A1 A2 B2 6 DSR DSR OE 7 RI RI GND DCD DCD 8 U2 GND GND - Figure 43 : UART interf ace application circuit with partial V.24 link (6 wire) in DTE/DCE serial communication (3.0 V DTE) Description Reference Manufacturer - Part Number 100 nF Capacitor Ceramic X7R 0402 10% 16 V Murata - C1, C2, C3, C4 GRM155R61A104KA01 15 U1 Voltage Translator Unidirectional Texas Instruments - SN74AVC4T774 15 SN74AVC2T245 U2 Unidirectional Voltage Translator - Texas Instruments Table 30 : UART application circuit components with partial V.24 link (6 - wire) in DTE/DCE serial communication (3.0 V DTE) 14 SARA must be set low - use the UART to Flow control is not supported by ‘ 0 0 ’ , ‘ 01 ’ and input - R410M 02B product versions , but the RTS ’ product versions . on ‘ 00 ’ and ‘ 01 ’ versions . The DTR ‘x input must be set low to have URCs presented over UART on ‘ 00 ’ , ‘ 01 ’ and 2 15 1.8 V supply V_INT supply can be also ramped up before 3 V DTE partial power down feature so that the ing provid oltage translator V - 16029218 116 of 74 Page - in - Design R11 UBX

75 - SARA System Integration Manual - R4/N4 series 16 Providing the TXD, RXD, RTS and CTS lines only lines is not required, or the lines are not available: If the functionality of the DSR , DCD , RI and DTR  Connect the module DTR input to GND using a 0  series resistor, since it may be useful to set DTR acti ve if not specifically handled, in particular to have URCs presented over the UART +CNMI AT [1] interface (see the SARA - R4/N4 series AT Commands Manual for the &D, S0, commands) Leave  DCD point on - lines of the module floating, with a test RI and DCD , DSR 232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be - If RS 232 standard. If a 1.8 V - This chip translates voltage levels from 1.8 V (module side) to the RS used. Application Processor is used, the circuit should be implemented as described in 44 . Figure Application Processor - SARA R4/N4 (1.8V DTE) (1.8V DCE) 0 Ω TP 12 TXD TxD Ω 0 TP 13 RXD RxD Ω 0 TP 10 RTS RTS Ω 0 TP 11 CTS CTS 9 DTR DTR 6 DSR DSR 7 RI RI 8 DCD DCD GND GND 44 Figure : UART interface application circuit with partial V.24 link (5 - wire) in the DTE/DCE serial communication (1.8V DTE) If a 3.0 V Application Processor (D TE) is used, then it is recommended to connect the 1.8 V UART interface of the module (DCE) by means of appropriate unidirectional voltage translators using the V_INT output as 1.8 V supply for the voltage translators on the module side, as in Figure 45 . module Application Processor R4/N4 - SARA (3.0V DTE) (1.8V DCE) Unidirectional 1V8 3V0 Voltage Translator TP VCCB VCCA 4 V_INT VCC C1 C2 DIR1 DIR3 Ω 0 TP 12 A1 B1 TXD TxD 0 Ω TP 13 A2 B2 RXD RxD 10 A3 B3 RTS RTS 11 B4 A4 CTS CTS DIR2 OE DIR4 GND U1 Ω 0 TP 9 DTR DTR 6 DSR DSR 7 RI RI TP 8 DCD DCD GND GND Figure 45 : UART interface application circuit with a partial V.24 link (5 - wire) in DTE/DCE serial communication (3.0 V DTE) Manufacturer Reference Description Part Number - - GRM155R61A104KA01 Murata C1, C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V 17 SN74AVC4T774 U1 Unidirectional Voltage Translator - Texas Instruments Table 31 : UART application circuit components with a partial V.24 link (5 - wire) in DTE/DCE serial communication (3.0 V DTE) 16 SARA Flow control is not supported by ‘ 00 ’ , ‘ 01 ’ and - R410M - 02B product versions , but the RTS input must be set low to use the UART product versions . ‘x ’ on ‘ 00 ’ and ‘ 01 ’ versions . The DTR input must be set low to have URCs presented over UART on ‘ 00 ’ , ‘ 01 ’ and 2 17 ing provid oltage translator V 1.8 V supply V_INT supply can be also ramped up before 3 V DTE partial power down feature so that the - in 16029218 - R11 Design - UBX Page 75 of 116

76 SARA System Integration Manual - R4/N4 series - 18 Providing the TXD and RXD lines only CTS , RTS , DSR , DCD If the functionality of the RI and DTR lines is not required in the application, or , the lines are not available, then:  Connect the module RTS input line to GND or to the CTS output line of the module, since the module requires active (low electrical level) if HW flow - control is enabled (AT &K3, which is the RTS default setting)  Connect the module DTR input line to GND using a 0  series resistor, because it is useful to set DTR active if not specifically handled, in particular to have URCs presented over the UART , [1] AT Commands Manual R4/N4 series - SARA (see +CNMI AT commands) &D, S0, interface - DSR , DCD and RI Leave lines of the module floating, with a test point on DCD  If RS - 232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be used. This chip translates voltage levels from 1.8 V (module side) to the RS - 232 standard. If a 1.8 V Application Processor (DTE) is used, the circuit that should be implemented as in Figure 46 . Application Processor R4/N4 - SARA (1.8V DCE) (1.8V DTE) 0 Ω TP 12 TXD TxD 0 Ω TP 13 RxD RXD Ω 0 TP 10 RTS RTS TP 11 CTS CTS 9 DTR DTR 6 DSR DSR 7 RI RI 8 DCD DCD GND GND 46 - wire : UART interface application circuit with a 3 link in the DTE/DCE serial communication (1.8V DTE) Figure n Processor (DTE) is used, then it is recommended to connect the 1.8 V UART If a 3.0 V Applicatio interface of the module (DCE) by means of appropriate unidirectional voltage translators using the e, as in V supply for the voltage translators on the module sid output as 1.8 V_INT module . 47 Figure Application Processor R4/N4 - SARA (3.0V DTE) (1.8V DCE) Unidirectional 1V8 3V0 Voltage Translator TP 4 VCCA VCCB V_INT VCC C1 C2 DIR1 Ω 0 TP 12 B1 A1 TxD TXD Ω 0 TP 13 A2 B2 RXD RxD DIR2 OE GND U1 0 Ω TP 10 RTS RTS TP 11 CTS CTS 9 DTR DTR 6 DSR DSR 7 RI RI DCD DCD 8 GND GND Figure : UART interface application circuit with a partial V.24 link (3 - wire) in DTE/DCE serial communication (3.0 V DTE) 47 Reference Description Part Number - Manufacturer C1, C2 Murata - GRM155R61A104KA01 100 nF Capacitor Ceramic X7R 0402 10% 16 V 19 SN74AVC2T245 U1 Unidirectional Voltage Translator - Texas Instruments Table 32 : UART application circuit components with partial V.24 link (3 - wire) in DTE/DCE serial communication (3.0 V DTE) 18 Flow control is not supported by ‘ 00 ’ , ‘ 01 ’ and SARA - R410M - 02B product versions , but the RTS input must be set low to use the UART . ‘x ’ product versions on ‘ 00 ’ and ‘ 01 ’ versions . The DTR input must be set low to have URCs presented over UART on ‘ 00 ’ , ‘ 01 ’ and 2 19 ing provid oltage translator V 1.8 V supply V_INT supply can be also ramped up before 3 V DTE partial power down feature so that the - in 16029218 - R11 Design - UBX Page 76 of 116

77 SARA - System Integration Manual - R4/N4 series Additional considerations utput of the DTE to If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V o - cost the corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low - up down / pull - solution, by means of an appropriate voltage divider. Consider the value of the pull CE) for the correct selection of the voltage divider resistance integrated at the input of the module (D values. Make sure that any DTE signal connected to the module is tri - stated or set low when the ion - down mode and during the module power - on sequence (at least until the activat module is in power V_INT of the up of circuits and allow a clean boot of the - supply output of the module), to avoid latch module (see the remark below). Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding - 3.0 V input of the Application Processor (DTE) can be implemented by means of an appropriate low cost non - inverting buffer with open drain output. The non - inverting buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the pull up integrated at each input - of the DTE (if any) and the baud rate required by the application for the appropriate selection of the ance value for the external pull resist up biased by the application processor supply rail. - on - pull data input line has an internal active TXD The ☞ the “00” and “02” product down enabled versions, and an internal active pull up enabled on the “01” product version. - apply voltage to any UART interface pin before the switch on of the UART supply source - not Do ☞ ), to avoid latch up of circuits and allow a clean boot of the module. If the external signals - V_INT channel digital connected to the cellular module cannot be tri - stated or set low, in sert a multi - - switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two circuit connections switch and set to high impedance before V_INT on . - ESD sensitivity rating of the UART interface pins is 1 kV (Human Body Model according - ☞ to JESD22 A114). Higher protection levels could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points. Guidelines for UART layout design 2.6.1.2 The UART serial interface requires the same consideration regarding electro - magnetic interference void coupling with RF line or sensitive analog as any other digital interface. Keep the traces short and a inputs, since the signals can cause the radiation of some harmonics of the digital data frequency. - in 16029218 - R11 Design - UBX Page 77 of 116

78 SARA System Integration Manual - R4/N4 series - 2.6.2 USB interface 2.6.2.1 Guidelines for USB circuit design and - naling. The lines are used in single lines carry the USB serial data and sig - USB_D The USB_D+ ended mode for full speed signaling handshake, as well as in differential mode for high speed signaling and data transfer. up or pull - USB pull lines as - USB_D and USB_D+ down resistors and external series resistors on - equired by the USB 2.0 specification are part of the module USB pins driver and do not need to be r [4] externally provided. input VUSB_DET The USB interface of the module is enabled only if a valid voltage is detected by the [1] Data Sheet R4/N4 series - SARA (see the ). Neither the USB interface nor the whole module is senses the USB supply voltage and absorbs few VUSB_DET input: the VUSB_DET supplied by the . microamperes Routing ble on the application device. USB pins to a connector, they will be externally accessi the very According to EMC/ESD requirements of the application, an additional ESD protection device with low capacitance should be provided close to accessible point on the line connected to this pin, as and Table 33 . described in 48 Figure ☞ The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22 - n be A114F). Higher protection level could be required if the lines are externally accessible and it ca achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402 - 140 ESD protection device) on the lines connected to these pins, close to accessible points. ectly connected to the USB host application processor without USB pins of the modules can be dir The additional ESD protections if they are not externally accessible or according to EMC/ESD requirements. USB HOST USB DEVICE SARA SARA - R4/N4 R4/N4 - PROCESSOR CONNECTOR 0 Ω Point - Test 17 17 VBUS VUSB_DET VUSB_DET VBUS 0 Ω Test Point - 29 29 USB_D+ USB_D+ D+ D+ 0 Ω Point - Test 28 28 - USB_D USB_D - D - D - D3 D1 D2 C1 C1 GND GND GND GND on circuits : USB Interface applicati 48 Figure Manufacturer Reference Description Part Number - C1 Murata - GRM155R61A104KA01 100 nF Capacitor Ceramic X7R 0402 10% 16 V - - Tyco Electronics 140 D1, D2, D3 Very Low Capacitance ESD Protection PESD0402 33 Components for USB application circuits Table : If the USB interface is enabled, the module does not enter the low power deep sleep mode: the ☞ external USB VBUS supply voltage needs to be removed from the VUSB_DET input of the module defined in 3GPP Rel.13 to let it enter the Power Savin . g Mode ☞ If the USB interface pins are not used, they can be left unconnected on the application board, but it is strongly recommended to provide accessible test points directly connected to the USB , VUSB_DET interface pins ( ). - USB_D , USB_D+ - in 16029218 - R11 Design - UBX Page 78 of 116

79 - SARA System Integration Manual - R4/N4 series 2.6.2.2 Guidelines for USB layout design / lines require accurate layout design to achieve reliable signaling at the high USB_D The USB_D+ - speed data rate (up to 480 Mb/s) supported by the USB serial interface. lines is specified by the Universal Serial Bus - The characteristic impedance of the / USB_D+ USB_D Revision 2.0 specification [4] . The most important parameter is the differential character istic impedance applicable for the odd - mode electromagnetic field, which should be as close as possible to  90 differential. Signal integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very long. Use the foll owing general routing guidelines to minimize signal quality problems: Route  - USB_D+ / USB_D lines as a differential pair lines as short as possible - USB_D /  Route USB_D+   ) is as close as possible to 90 Ensure the differential characteristic impedance (Z 0   ) is as close as possible to 30 Ensure the common mode characteristic impedance (Z CM similar to RF transmission lines, being them coupled  USB_D / USB_D+ Consider design rules for - e of layout, and route on strip or buried stripline: avoid any stubs, abrupt chang - differential micro clear PCB area provide two examples of coplanar waveguide designs with differential 50 Figure and 49 Figure and common mode characteristic impedance close to 30  characteristic impedance close to 90 .  layer PCB stack - up herein described, the - The first transmission line can be implemented in case of 4 - up herein described. second transmission line can be implemented in case of 2 - layer PCB stack m μ 350 μ μ 400 m μ m 350 m 400 m μ 400 L1 Copper 35 μ m 4 dielectric FR 270 - m μ μ m 35 L2 Copper 4 dielectric μ 760 m - FR L3 Copper m μ 35 m μ FR - 4 dielectric 270 μ 35 m L4 Copper layer board layup , for the described 4  close to 30 and Z  to 90 close - : Example of USB line design, with Z 49 Figure 0 CM 740 m μ 410 m 410 m μ 410 m μ μ 740 μ m L1 Copper 35 μ m FR - 4 dielectric m 1510 μ 35 μ m L2 Copper  Figure 50 : Example of USB line design, with Z layer board layup close to 90 - and Z  close to 30 , for the described 2 CM 0 - in 16029218 - R11 Design - UBX Page 79 of 116

80 SARA - System Integration Manual - R4/N4 series erface SPI int 2.6.3 Guidelines for SPI circuit design 2.6.3.1 ☞ product versions: the SPI interface 01”, “02” and “52” supported by “00”, “ is not The SPI interface pins should not be driven by any external device. 2.6.4 SDIO interface Guidelines for SDIO circuit design 2.6.4.1 ☞ product versions: the SDIO 01”, “02” and “52” supported by “00”, “ is not interface The SDIO interface pins should not be driven by any external device. 2 DDC (I C) interface 2.6.5 2 C) circuit design Guidelines for DDC (I 2.6.5.1 2 2 DDC (I supported by “00” and “01” product versions: the DDC (I ☞ C) interface pins is not C) interface should not be driven by any external device. 2 bus master interface can be used to communicate with u The DDC I C - blox GNSS receivers and other - 2 external I C - bus slaves as an audio cod ec. 2 C bus specifications The pins of the module are open drain output as per I SCL and SDA , and they [9] - V_IN up resistors to the have internal pull T 1.8 V supply rail of the module, so there is no need of up resistors on the external application board. additional pull - 2 C specifications (1.0 ☞ Capacitance and series resistance must be limited on the bus to match the I SDA and SCL on the lines): route connections as short as s is the maximum allowed rise time μ possible. 2 ☞ ESD sensitivity rating of the DDC (I A114). C) pins is 1 kV (Human Body Model according to JESD22 - Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the pins are not used as DDC bus interface, they can be left unconnected. ☞ - in 16029218 - R11 Design - UBX Page 80 of 116

81 R4/N4 series SARA System Integration Manual - - blox 1.8 V GNSS receivers - Connection with u Figure shows an application circuit for connecting the cellular module to a u 51 - blox 1.8 V GNSS receiver: and The  SCL pins of the cellular module are directly connected to the related pins of the u - SDA up resistors are not needed, as they are already integrated blox 1.8 - V GNSS receiver. External pull in the cellular module. - pin is connected to the active r that supplies the GPIO2 The high enable pin of the voltage regulato  V GNSS receiver providing the “GNSS supply enable” function. A pull - u blox 1.8 down resistor is - provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. The onnected to the TXD1 pin of the u - blox 1.8  V GNSS receiver providing the GPIO3 pin is c additional “GNSS Tx data ready” function. - u SARA - R4/N4 blox GNSS (except ’00’,’01’ versions) 1.8 V receiver GNSS LDO VMAIN 1V8 Regulator IN OUT VCC GNSS supply enabled SHDN 23 GPIO2 C1 GND R1 U1 26 SDA2 SDA 27 SCL SCL2 GNSS data ready 24 TxD1 GPIO3 modules to u Figure 51 : Application circuit for connecting SARA - R4/N4 series blox 1.8 V GNSS receivers - Reference Description Part Number - Manufacturer - 0747KL Yageo Phycomp - RC0402JR Resistor 0402 5% 0.1 W R1 47 k Ω See GNSS receiver Hardware Integration Manual U1 Voltage Regulator for GNSS receiver 34 Table blox 1.8 V GNSS receivers - modules to u R4/N4 series - SARA : Components for connecting blox 1.8 V GNSS receivers, see - For additional guidelines regarding the design of applications with u the Hardware Integration Manual of the u - blox GNSS receivers. Connection with u - blox 3.0 V GNSS rece ivers - shows an application circuit for connecting the cellular module to a u 52 Figure blox 3.0 V GNSS receiver: r module are not tolerant up to 3.0 V, the connection to the and SDA As the  pins of the cellula SCL 2 2 C bus - related I blox 3.0 V GNSS receiver must be provided using a suitable I - C pins of the u Bidirectional Voltage Translator (e.g. TI TCA9406, which additionally provides the partial power down V_INT 1.8 V cellular feature so that the GNSS 3.0 V supply can be ramped up before the supply). External pull - up resistors are not needed on the cellular module side, as they are already integrated in the cellular module. ve -  The - high enable pin of the voltage regulator that supplies the u GPIO2 is connected to the acti - blox 3.0 V GNSS receiver providing the “GNSS supply enable” function. A pull down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state. - in 16029218 - R11 Design - UBX Page 81 of 116

82 SARA System I ntegration Manual - R4/N4 series -  pin of the u TXD1 pin is connected to the blox 3.0 V GNSS receiver providing the GPIO3 The - additional “GNSS Tx data ready” function, using a suitable Unidirectional General Purpose Voltage itionally provides the partial power down feature so Translator (e.g. TI SN74AVC2T245, which add that the 3.0 V GNSS supply can be also ramped up before the 1.8 V cellular supply. V_INT u blox GNSS - SARA - R4/N4 (except ‘00’,’01’ versions) 3.0 V receiver 3V0 VMAIN Regulator LDO IN OUT VCC GNSS supply enabled 23 SHDNn GND GPIO2 C1 R3 U1 bus Bidirectional - I2C 1V8 Voltage Translator VCCB 4 VCCA V_INT C3 C2 OE R1 R2 SDA_A SDA_B 26 SDA2 SDA SCL_B 27 SCL_A SCL2 SCL GND U2 Unidirectional 1V8 3V0 Voltage Translator VCCA VCCB C4 C5 DIR1 GNSS data ready 24 B1 A1 GPIO3 TxD1 B2 A2 DIR2 OEn GND U3 - - modules to u Figure SARA R4/N4 series : Application circuit for connecting 52 blox 3.0 V GNSS receivers Part Number Description Reference Manufacturer - 4.7 k Ω Resistor 0402 5% 0.1 W R1, R2 RC0402JR - 074K7L - Yageo Phycomp 47 k Yageo Phycomp R3 Ω Resistor 0402 5% 0.1 W RC0402JR - 0747KL - Murata C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Voltage Regulator for GNSS receiver and See GNSS receiver Hardware Integration Manual U1, C1 related output bypass capacitor Texas Instruments - TCA9406DCUR Bidirectional Voltage Translator bus - I2C U2 Texas Instruments U3 Generic Unidirectional Voltage Translator SN74AVC2T245 - SARA Table - blox 3.0 V GNSS receivers modules to u R4/N4 series - : Components for connecting 35 - For additional guidelines regarding the design of applications with u blox 3.0 V GNSS receivers see the Hardware Integration Manual of the u - blox GNSS receivers. 2 2.6.5.2 Guidelines for DDC (I C) layout design 2 C) serial interface requires the same consideration regarding electro (I DDC The magnetic - interference as any other digital interface. Keep the traces short and avoid coupling with RF line or , since the signals can cause the radiation of some harmonics of the digital sensitive analog inputs data frequency. 2.7 Audio Guidelines for Audio circuit design 2.7.1 2 product versions: the I 01”, “02” and “52” supported by “00”, “ S interface pins should Audio ☞ is not not be driven by any external device. - in 16029218 - R11 Design - UBX Page 82 of 116

83 R4/N4 series SARA System Integration Manual - - 2.8 General Purpose Input/Output Guidelines for GPIO circuit design 2.8.1 A typical usage of SARA - R4/N4 series modules’ GPIOs can be the following: 36 below)  Network indication provided over GPIO1 pin (see Figure 53 / Table 2.6.5 pin (see section GPIO2 GNSS supply enable function provided by the  ) 2.6.5 )  GNSS Tx data ready function provided by the GPIO3 pin (see section  pin (see section ) 1.6.1 GPIO Module operating status indication provided by a 2.5 pin (see / Table 28 in section Figure 39 )  SIM card detection provided over GPIO5 3V8 R4/N4 - SARA R3 DL1 R1 Network Indicator 16 GPIO1 T1 R2 Figure : Application circuit for network indication provided over GPIO1 53 - Part Number Description Reference Manufacturer Various manufacturers R1 10 k  Resistor 0402 5% 0.1 W R2 Various manufacturers 47 k  Resistor 0402 5% 0.1 W Various manufacturers R3 Resistor 0402 5% 0.1 W 820  C190KRKT - DL1 LED Red SMT 0603 on Technology Corporation - Lite - LTST T1 NPN BJT Transistor BC847 - Infineon 36 : Components for network indication application circuit Table resistor  integrated resistor in the base pin or otherwise put a 10 k Use transistors with at least an ☞ on the board in series to the GPIO of modules. R4/N4 series - SARA - Do ), V_INT supply ( on of the GPIOs ☞ before the switch of the module not apply voltage to any GPIO - to avoid latch up of circuits and allow a clean module boot. If the external signals connected to the module cannot be tri - - channel digital switch (e.g. TI stated or set low, insert a multi circuit connections and set to high - SN74CB3Q16244, TS5A3159, TS5A63157) between the two impedance before V_INT - on switch . - ☞ A114). ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22 Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points. If the GPIO pins are not used, they can be left unconnected on the application board. ☞ 2.8.2 Guidelines for general purpose input/output layout desig n The general purpose inputs / outputs pins are generally not critical for layout. - in 16029218 - R11 Design - UBX Page 83 of 116

84 - SARA - System Integration Manual R4/N4 series Reserved pins (RSVD) 2.9 R4/N4 series - SARA modules have pins reserved for future use, marked as RSVD . RSVD RSVD pins are to be left unco nnected on the application board, except for the pin number All the that can be externally connected to ground. 33 2.10 Module placement VCC An optimized placement allows a minimum RF line’s length and closer path from DC source for . Make sure that the module, an alog parts and RF circuits are clearly separated from any possible source of radiated energy. In particular, digital circuits can radiate digital frequency harmonics, which Magnetic Interference that affects the module, analog parts and can produce Electro - RF circuits’ performance. Implement suitable countermeasures to avoid any possible Electro - Magnetic Compatibility issue. Make sure that the module, RF and analog parts / circuits, and high speed digital circuits are clearly Magnetic Interference, - separated from any sensitive pa rt / circuit which may be affected by Electro Magnetic Compatibility issue. - or employ countermeasures to avoid any possible Electro Make sure that the module is placed in order to keep the antenna as far as possible from VCC supply l 28 ) Figure (refer to ine and related parts , from high speed digital lines (as USB) and from any possible noise source. the module and any external part: clearance of at least 0.4 mm per Provide enough clearance between side is recommended to let suitable mounting of the parts. The heat dissipation during continuous transmission at maximum power can significantly raise ☞ board below the - modules: avoid R4/N4 series ase the temperature of the application b SARA - placing temperature sensitive devices close to the module. - in 16029218 - R11 Design - UBX Page 84 of 116

85 R4/N4 series SARA System Integration Manual - - Module footprint and paste mask 2.11 for Figure describe the suggested footprint (i.e. copper mask) and paste mask layout 37 Table and 54 SARA modules: the proposed land pattern layout reflects the modules’ pins layout, while the proposed stencil apertures layout is slightly different (see the F’’, H’’, I’’, J’’, O’’ parameters compared to the F’, H’, I’, J’, O’ ones). re The Non Solder Mask resist Solder the pad type is recommended over (NSMD) Mask Defined sist as it μ mask opening 50 resist the solder m larger per side than s implement pad type, (SMD) Defined the corresponding copper pad. m, according to application μ paste is 150 ing solder thickness of the stencil for the The recommended production process requirements. B B Pin Pin 1 1 ANT pin ANT pin G E G J’ E J’’ H’’ E H’ E I’ I’’ D D K K M1 M1 M1 M1 M2 M2 O’’ O’ G G O’’ O’ Stencil: 150 A A H’ H’’ m μ J’’ J’ K K D D F’ F’’ F’ F’’ L N L N L L (application board top view) R4/N4 series modules suggested footprint and paste mask - SARA : Figure 54 Value Parameter Value Parameter Parameter Value 2.75 mm G 1.10 mm K A 26.0 mm 0.80 mm H’ 16.0 mm B 2.75 mm L 0.75 mm 3.00 mm H’’ C M1 1.80 mm 1.50 mm 3.60 mm M2 D 2.00 mm I’ E 2.10 mm N 1.55 mm I’’ 2.50 mm 0.30 mm F’ 1.10 mm O’ J’ 1.05 mm O’’ 1.05 mm J’’ 1.00 mm F’’ 0.35 mm modules suggested footprint and paste mask dimensions Table 37 : SARA - R4/N4 series ☞ These are recommendations only and not specifications. The exact copper, solder and paste mask geometries, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer. - 16029218 116 of 85 Page - n i - Design R11 UBX

86 - SARA - System Integration Manual R4/N4 series Thermal guidelines 2.12 Data Sheet R4/N4 series - SARA is specified in the temperature range The module operating ☞ . ] [1 The most critical condition concerning module thermal performance is the uplink transmission at maximum power (data upload in connected mode), when the baseband processor runs at full speed, radio circuits are all active and the RF power amplifier is drive n to higher output RF power. This scenario is not often encountered in real networks (for example, see the Terminal Tx Power distribution for WCDMA, taken from operation on a live network, described in the GSMA TS.09 Battery Life Measurement and Current Co ); however the application should be [10] nsumption Technique correctly designed to cope with it. modules - SARA During transmission at maximum RF power the R4/N4 series generate thermal power that may exceed 0.5 W: this is an indicative value since the exact generated power strictly depends g frequency band, etc. on operating condition such as the actual antenna return loss, the transmittin The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application. - ) depends on the module The spreading of the Module - A - th,M Ambient thermal resistance (R to operating condition. Th e overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface. Ambient thermal resistance value and the re - The Module lative increase of module temperature - ☞ to will differ according to the specific mechanical deployments of the module, e.g. application PCB with different dimensions and characteristics, mechanical shells enclosure, or forced air flow. to The increase of the therm - al dissipation, i.e. the reduction of the Module Ambient thermal - resistance, will decrease the temperature of the modules’ internal circuitry for a given operating ambient temperature. This improves the device long - term reliability in particular for app lications operating at high ambient temperature. Recommended hardware techniques to be used to improve heat dissipation in the application: and connect each ground pin with solid ground layer of the application GND Connect each  PCB area of the multilayer application PCB with complete thermal via stacked down to main ground layer.  Provide a ground plane as wide as possible on the application board. rformance of the module including a  Optimize antenna return loss, to optimize overall electrical pe decrease of module thermal power. Optimize the thermal design of any high - power components included in the application, such as  linear regulators and amplifiers, to optimize overall temperature distribution in the applic ation.  Select the material, the thickness and the surface of the box (i.e. the mechanical enclosure) of the application device that integrates the module so that it provides good thermal dissipation. to - Ambient thermal re - sistance implemented by correct Beside the reduction of the Module application hardware design, the increase of module temperature can be moderated by a software implementation: correspondingly correct application  Enable power saving configuration using the AT+CPSMS command onnected mode for a given time period and then disable it for a time period long  Enable module c enough to adequately mitigate the temperature increase. - in 16029218 - R11 Design - UBX Page 86 of 116

87 SARA - System Integration Manual R4/N4 series - module integration R4/N4 series - SARA Schematic for 2.13 2.13.1 - modules R4/N4 series SARA Schematic for - Figure x2 “00”, “01” or “ R4/N4 series ” product SARA is an example of a schematic diagram where a 55 interfaces and functions. module le version is integrated into an application board using all availab SARA - R4/N4 External Connector 15pF 33pF antenna 3V8 VCC 51 ANT 56 VCC 52 39nH 68nH 53 VCC 100nF 15pF 68pF 100uF 10nF GND 10k ANT_DE 62 T 27pF ESD SIM Card Application V_INT Holder Processor 1k TP TP 15 PWR_ON 4 SW1 V_INT Open drain 42 SW2 GPIO5 output CCVCC (C1) 41 VSIM TP CCVPP (C6) 18 RESET_N Open CCIO (C7) 39 SIM_IO drain output 38 SIM_CLK CCCLK (C3) CCRST (C2) SIM_RST 40 GND (C5) USB 2.0 host 47pF 47pF 100nF 47pF 47pF ESD ESD ESD ESD ESD ESD 470k TP Ω 0 17 VBUS VUSB_DET ‘00’ and ‘01’ product version Not supported by Ω 0 TP u blox GNSS - - D 28 USB_D - 3.0 V receiver TP Ω 0 LDO Regulator 3V8 3V0 D+ 29 USB_D+ VCC OUT IN 100nF GND GND GND SHDNn 23 GPIO2 47k TCA9406 1.8 V DTE V_INT I2C Voltage Translator Ω 0 TP 12 TXD TXD TP Ω 0 VCCB VCCA RXD 13 RXD 100nF 100nF OE 4.7k 4.7k RTS 10 RTS SDA2 SDA_B SDA SDA_A 26 11 CTS CTS 27 SCL_A SCL SCL_B SCL2 GND DTR 9 DTR 6 DSR DSR SN74AVC2T245 7 RI RI V_INT 3V0 Voltage Translator DCD 8 DCD VCCB VCCA GND GND 100nF 100nF DIR1 24 TxD1 GPIO3 A1 B1 RSVD B2 25 GPIO4 EXTINT0 A2 DIR2 OEn GND SDIO_D2 44 19 GPIO6 45 SDIO_CLK SDIO_CMD 46 I2S_TXD / SPI_CS 35 47 SDIO_D0 SPI_MISO 37 I2S_RXD / 3V8 SDIO_D3 48 / SPI_CLK 36 I2S_CLK Network I2S_WA / 49 SDIO_D1 SPI_MOSI 34 Indicator GPIO1 16 GND 20 : Example of schematic diagram to integrate a SARA - R4/N4 series Figure 55 module using all available interfaces 20 Flow control is not supported by ‘ 00 ’ use the UART ‘ 01 ’ and SARA - R410M - 02B product versions , but the RTS input mus t be set low to , . ‘ , ’ 00 ‘ on be set low to have URCs presented over UART product versions ’ DTR must input 2 ‘x ’ and 01 on ‘ 00 ’ and ‘ 01 ’ versions . The - in 16029218 - R11 Design - UBX Page 87 of 116

88 SARA - System Integration Manual - R4/N4 series list in check - Design 2.14 in checklist. - This section provides a design 2.14.1 Schematic checklist The following are the most important points for a simple schematic check: VCC DC supply must provide a nominal voltage at  pin within the operating range limits.  DC supply must be capable of supporting the highest peak / pulse current consumption values and the maximum averaged current consumption values in connected mode, as specified in SARA . the - R4/N4 series Data Sheet [1] VCC  voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors, in particular if the application device integ rates an internal antenna.  Do not apply loads which might exceed the limit for maximum available current from V_INT supply. Check that voltage level of any connected pin does not exceed the relative operating range.   - SARA Provide accessible test points directly connected to the following pins of the R4/N4 modules: series and RESET_N for diagnostic purposes. , V_INT PWR_ON  Capacitance and series resistance must be limited on each SIM s ignal to match the SIM specifications.  Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible. - Check UART signals direction, as the modules’ signal names follow the ITU  T V.24 . [5] Recommendation Capacitance and series resistance must be limited on each high speed line of the USB  interface.  irectly connected to the USB It is strongly recommended to provide accessible test points d - and pins). USB_D+ , VUSB_DET USB_D interface pins (  integrated resistor in the base pin or otherwise put a 10 k Use transistors with at least an  resistor on the board in series to the GPIO when those are used to drive LEDs. Provide adequate precautions for EMC / ESD immunity as required on the application board.   modules before ny generic digital interface pin of SARA - R4/N4 series Do not apply voltage to a on of the generic digital interface supply source ( - the switch V_INT ).  All unused pins can be left unconnected. Layout checklist 2.14.2 The following are the most important points for a simple layout check:  nominal characteristic impedance of the RF transmission line connected to the  Check 50 port (antenna RF interface). ANT M Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SI  speed digital lines such as USB, and other data lines) signals, high - . Optimize placement for minimum length of RF line.   R4/N4 series - Check the footprint and paste mask designed for module as illustrated in SARA section . 2.11  VCC line should be enough wide and as short as possible. Route  VCC nd other sensitive analog ) a supply line away from RF line / part (refer to Figure 28 lines / parts. - in 16029218 - R11 Design - UBX Page 88 of 116

89 SARA - System Integrati on Manual - R4/N4 series bypass capacitors in the picoFarad range should be placed as close as possible t VCC The  o the pins, in particular if the application device integrates an internal antenna. VCC pin with application board solid ground GND Ensure an optimal grounding connecting each  layer.  Use as many vias as possible to connect the ground planes on multilayer a pplication board, providing a dense line of vias at the edges of each ground area, in particular along RF and high speed lines.  Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity.  ld meet the characteristic impedance requirement (90 traces shou - USB_D+  USB_D /  differential and 30 common mode) and should not be routed close to any RF line / part. 2.14.3 Antenna checklist characteristic impedance with V.S.W Antenna termination should provide 50  R at least less .  than 3:1 (recommended 2:1) on operating bands in deployment geographical area.  he antenna producer for correct antenna installation and Follow the recommendations of t deployment (PCB layout and matching circuitry).  Ensure compliance with any regulatory agency RF radiation requirement, as reported in 4.3.1 4.2.2 section for Canada. for United States and in section he cellular antenna and any other antennas or transmitters Ensure high isolation between t  present on the end device. - in 16029218 - R11 Design - UBX Page 89 of 116

90 - SARA - System Integration Manual R4/N4 series Handling and soldering 3 No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. ☞ Packaging, shipping, storage and moisture preconditio ning 3.1 For information pertaining to reels / tapes, Moisture Sensitivity levels (MSD), R4/N4 series - SARA - shipment and storage information, as well as drying for preconditioning, see the R4/N4 series SARA [1] Data Sheet . [15] blox Package Information Guide - and the u 3.2 Handling R4/N4 series SARA The Static Discharge (ESD) sensitive devices. - modules are Electro - ⚠ the module. Ensure ESD precautions are implemented during handling of Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. The term is usually used in the electron ics and other industries to describe momentary unwanted currents that may cause damage to electronic equipment. s R4/N4 serie - modules (as Human Body Model according to The ESD sensitivity for each pin of SARA ) is specified in the A114F Data Sheet JESD22 . [1] R4/N4 series - SARA - ESD prevention is based on establishing an Electrostatic Protective Area (EPA). The EPA can be a small working station or a large manufacturing area. The main principle of an EPA is that there are no highly charging materials near ESD sensitive electronics, all conductive materials are grounded, up on ESD sensitive electronics is prevented. International - unded, and charge build workers are gro standards are used to define typical EPA and can be obtained for example from the International te (ANSI). Electrotechnical Commission (IEC) or the American National Standards Institu In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the R4/N4 series - SARA modules: Unless there is a galvanic coupling between the local GND (i.e . the work table) and the PCB GND,  then the first point of contact when handling the PCB must always be between the local GND and PCB GND.  Before mounting an antenna patch, connect the ground of the device.  When handling the module, do not come into contac t with any charged capacitors and be careful when contacting materials that can develop charges (e.g. patch antenna, coax cable, soldering iron).  To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If risk that such exposed antenna area is touched in a non ESD protected work area, - there is any implement adequate ESD protection measures in the design.  safe - When soldering the module and patch antennas to the RF pin, make sure to use an ESD soldering iron. Handling and soldering 16029218 - R11 - UBX Page 90 of 116

91 - SARA - System Integration Manual R4/N4 series Soldering 3.3 Soldering paste 3.3.1 R4/N4 series modules, as it does not - SARA "No Clean" soldering paste is strongly recommended for require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria. tronics) OM338 SAC405 / Nr.143714 (Cookson Elec Soldering Paste: 95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper) Alloy specification: 95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper) 217 °C Melting Temperature: μ 150 Stencil Thickness: m for base boards of the soldering paste depends on the approved manufacturing procedures. The final choice - mask geometry for applying soldering paste should meet the recommendations in section The paste 2.11 . ☞ The quality of the solder joints should meet the appropriate IPC specification. 3.3.2 Reflow soldering soldering oven is strongly recommended for - the modules over - R4/N4 series A convection type SARA infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color. temperature profiling for mass soldering (reflow and wave) 7530A Guidelines for - Consider the ”IPC processes”. Reflow profiles are to be selected according to the following recommendations. ⚠ Failure to observe these recommendations can result in severe damage to the device! Preheat phase Initial heating of component leads and balls. Residual humidity will be dried out. Note that this preheat phase will not replace prior baking procedures. Temperature rise rate: max 3 °C/s If the temperature rise is too rapid in the preheat phase it  may cause exce ssive slumping. If the preheat is insufficient, rather large solder balls tend to 120 s  Time: 60 – be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. If the temperat +200 °C - - End Temperature: +150  melting tends to be ure is too low, non caused in areas containing large heat capacity. Heating/ reflow phase The temperature rises above the liquidus temperature of +217 °C. Avoid a sudden rise in temperature as the slump of the paste could become worse. - Limit time above +217 °C liquidus temperature: 40  60 s  Peak reflow temperature: +245 °C Handling and soldering 16029218 - R11 - UBX Page 91 of 116

92 - SARA System Integration Manual - R4/N4 series Cooling phase A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle. Temperature fall rate: max 4 °C/s  To avoid falling off, modules should be placed on the topside of the motherboard during soldering. ☞ The soldering temperat ure profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc. ⚠ Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module. Preheat Cooling Heating [°C] Peak Temp. 245°C [°C] 250 250 Liquidus Temperature 217 217 200 200 40 - 60 s End Temp. max 4°C/s 150 - 200°C 150 150 60 - 120 s max 3°C/s Typical Leadfree 100 100 Soldering Profile 50 50 Elapsed time [s] Figure : Recommended soldering profile 56 ☞ The modules must not be soldered with a damp heat process. 3.3.3 Optical inspection e module, inspect it optically to verify that is correctly aligned and centered. it After soldering th Cleaning 3.3.4 Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process.  y effects where water is absorbed in the gap between the Cleaning with water will lead to capillar baseboard and the module. The combination of residues of soldering flux and encapsulated water like interconnections between neighboring pads. Water will also leads to short circuits or resistor - ge the sticker and the ink - jet printed text. dama  Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into wash inspections. The solvent will also the two housings, areas that are not accessible for post - damage the sti cker and the ink - jet printed text.  Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators. For best results, use a "no clean" soldering paste and eliminate the cleaning step after the soldering. UBX Handling and soldering 1 6029218 - R11 - Page 92 of 116

93 SARA - System Integration Manual - R4/N4 series 3.3.5 Repeated reflow solderi ng Repeated reflow soldering processes and soldering the module upside - down are not recommended . Boards with components on both sides may require two reflow cycles. In this case, the module should always be placed on the side of the board that is submitted into the last reflow cycle. The reason for this (besides others) is the risk of the module falling off due to the significantly higher weight in relation to other components . - - SARA blox gives no warranty against damages to the modules caused by R4/N4 series ☞ u performing more than a total of two reflow soldering processes (one reflow soldering process to mount the module, plus one reflow soldering process to mount other R4/N4 series parts). SARA - Wave soldering 3.3.6 must not be soldered with a wave soldering process. SARA R4/N4 series LGA modules - mount technology - hole technology (THT) components and surface - Boards with combined through ave soldering to solder the THT components. No more than one wave (SMT) devices require w module already populated on it. R4/N4 series - SARA soldering process is allowed for a board with a result in severe damage to the device! ⚠ Performing a wave soldering process on the module can SARA modules caused by blox gives no warranty against damages to the R4/N4 series ☞ u - - performing more than a total of two soldering processes (one reflow soldering process to mount R4/N4 series - e th SARA module, plus one wave soldering process to mount other THT parts on the application board). 3.3.7 Hand soldering Hand soldering is not recommended. Rework 3.3.8 Rework is not recommended. on the module itself, e.g. replacing individual components. Such actions Never attempt a rework ☞ immediately terminate the warranty. 3.3.9 Conformal coating ® Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products. These materials aff ect the HF properties of the cellular modules and it is important to prevent them from flowing into the module. The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating. ☞ Conformal Coating of the module will void the warranty. 3.3.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the cellular modules before implemen ting this in production. Casting will void the warranty. ☞ Handling and soldering 16029218 - R11 - UBX Page 93 of 116

94 SARA - System Integration Manual R4/N4 series - Grounding metal covers 3.3.11 Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous grou nd pins should be sufficient to provide optimum immunity to interference and noise. - u ☞ blox gives no warranty for damages to the cellular modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers. 3.3.12 Use of ultras onic processes The modules contain components which are sensitive to ultrasonic waves. Use of any cellular ultrasonic processes (cleaning, welding etc.) may cause damage to the module. ☞ u - blox gives no warranty against damages to the cellular modules caused by any ultrasonic processes. 116 R11 - 16029218 - Handling and soldering UBX of 94 Page

95 SARA System Integration Manual - R4/N4 series - 4 Approvals 4.1 Product certification approval overview Product certification approval is the process of certifying that a product has passed all tests and s”, that can be divided into: criteria required by specifications, typically called “certification scheme Regulatory certification s  Country o specific approval required by local government in most regions and countries, as: -  CE (Conformité Européenne) marking for European Union  FCC (Federal Communications Commission) approval for the United States  s Industry certification - specific approval verifying interoperability between devices and networks: o Telecom industry  GCF (Global Certification Forum)  PTCRB (PCS Type Certification Review Board)  Operator certification s o Operator - specific approv als required by some mobile network operator, such as:  AT&T network operator in United States  Verizon Wireless network operator in United States . 38 Table are summarized in approvals ’ SARA - R4/N4 series modules SARA Certification SARA - R404M SARA - R410M - 01B SARA - R410M - 02B - R410M - 52B SARA - R412M - 02B SARA - N410 - 02B PTCRB LTE Cat M1 Bands LTE Cat NB1 Bands LTE Cat M1, NB1 Bands LTE Cat M1, NB1 Bands LTE Cat M1 Bands 2, 3, 4, 5, 8, 12, 13, 20, 28 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12 2, 4, 5, 12 2G Bands 850, 900, 1800, 1900 LTE Cat M1, NB1 Bands LTE Cat M1, NB1 Bands CE Europe 3, 8, 20 3, 8, 20 2G Bands 900, 1800 LTE Cat M1, NB1 Bands LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat NB1 Bands FCC US LTE Cat M1 Band LTE Cat M1 Bands 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12 2, 4, 5, 12, 13 13 2G Bands 850, 1900 XPYUBX18ZO01 XPY2AGQN4NNN XPY2AGQN4NNN FCC ID XPY2AGQN1NNN XPY2AGQN4NNN XPY2AGQN4NNN ISED Canada LTE Cat M1 Bands LTE Cat M1, NB1 Bands LTE Cat NB1 Bands LTE Cat M1 Bands LTE Cat M1, NB1 Bands 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12, 13 2, 4, 5, 12 2, 4, 5, 12, 13 2G Bands 850, 1900 - 8595A 2AGQN4NNN 2AGQN4NNN - 8595A - 8595A 2AGQN4NNN - UBX18ZO01 ISED ID 8595A - 2AGQN4NNN 8595A M1 Bands IFT Mexico 2, 4, 5, 12 LTE Cat M1 Bands RCM Australia 3, 5, 8, 28 LTE Cat NB1 Bands NCC Taiwan LTE Cat M1, NB1 Bands 3, 8, 28 3, 8, 28 LTE Cat M1 Bands Verizon LTE Cat M1 Band 4, 13 13 LTE Cat M1 Bands AT&T LTE Cat M1 Bands LTE Cat M1 Bands LTE Cat M1 Bands 2, 4, 5, 12 2, 4, 5, 12 2, 4, 5, 12 2, 4, 5, 12 LTE Cat NB1 Bands T - Mobile 2, 4, 5, 12 Bell LTE Cat M1 Bands 2, 4, 5, 12 LTE Cat M1 Bands Telus LTE Cat M1 Bands 2, 4, 5, 12 2, 4, 5, 12 LTE Cat M1 Bands Telstra 3, 5, 8, 28 SARA R4/N4 series modules, with related RAT and - bands Table 38 : Summary of certification approvals achieved for the ☞ For the complete list and specific details regar ding the certification approvals available for all the ordering numbers ’ modules R4/N4 series - SARA different , including certificates of compliancy, the u please contact blox office or sales representative nearest you. - - 16 029218 116 of 95 Page Approvals R11 - UBX

96 SARA - System Integration Manual - R4/N4 series take care of The manufacturer of the end module R4/N4 series - RA SA device that integrates a - must all certification approvals required by the specific integrating device to be deployed in the market. The required certifica tion scheme approvals and relative testing specifications applicable to the end - device that integrates a SARA - R4/N4 series module differ depending on the country or the region be deployed, on the relative vertical market of the device, where the integrating device is intended to on type, features and functionalities of the whole application device, and on the network operators where the device is intended to operate. The SARA - R4/N4 series modules from “02” product versions onwards include the capability to configure the device by selecting the operating Mobile Network Operator Profile, Radio Access . In the bands mands Manual , see the +UMNOPROF, R4/N4 series - SARA [2] Technology, and AT Com +URAT, and +UBANDMASK AT commands. device - blox reminds manufacturers of the end - As these configuration decisions are made, u R4/N4 series - SARA integrating the “02” product versions onwards of modules to take care of compliance with all the certification a pprovals requirements applicable to the specific integrating device to be deployed in the market. R4/N4 series - while starting Check the appropriate applicability of the ☞ SARA module’s approvals the re - the certification process o f the device integrating the module: blox cellular - se of the u u module’s approval can significantly reduce the cost and time to market of the application device certification. ☞ module and the SARA - R4/N4 series The certification of the application device that integrates a compliance of the application device with all the applicable certification schemes, directives and standards are the sole responsibility of the application device manufacturer. modules are certified according to all capabilities and options stated in the R4/N4 series - SARA Protocol Implementation Conformance Statement document (PICS) of the module. The PICS, according to the 3GPP TS 36.521 [12] ment of the implemented , is a state [13] 2 2 and 3GPP TS 36.523 - - and supported capabilities and options of a device. ☞ modules must be SARA - R4/N4 series The PICS document of the application device integrating updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device. For more details SARA - R4/N4 series AT regarding the AT commands settings that affect the PICS, see the Comm . [1] ands Manual Check the specific settings required for mobile network operators approvals as they may differ ☞ from the AT commands settings defined in the module as integrated in the application device. Approvals 16029218 - R11 - UBX Page 96 of 116

97 SARA System Integration Manual - R4/N4 series - US Federal Communications Commission notice 4.2 United States Federal Communications Commission (FCC) IDs: XPY2AGQN1NNN  u - blox SARA - R404M cellular modules: R410M XPY2AGQN4NNN  u - blox SARA - and SARA - N410 cell ular modules:  XPYUBX18ZO01 R412M cellular modules: - blox SARA - u Safety warnings review the structure 4.2.1 in. The requirements for fire enclosure must be evaluated in the end  Equipment for building - product  The clearance and creepage current dist ances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module  Excessive sound pressure from earphones and headphones can cause hearing los s  No natural rubbers, hygroscopic materials, or materials containing asbestos are employed  4.2.2 Declaration of Conformity This device complies with Part 15 of the FCC rules. Operation is subject to the following two conditions: this device may not cause harmful interference  this device must accept any interference received, including interference that may cause  undesired operation ⚠ Radiofrequency radiation exposure information: this equipment complies with the radiation led environment for fixed and mobile use conditions. exposure limits prescribed for an uncontrol cm between the This equipment should be installed and operated with a minimum distance of 20 - located or radiator and the body of the user or nearby persons. This transmitter must not be co operating in c onjunction with any other antenna or transmitter except as authorized in the certification of the product. - R4/N4 series ⚠ modules (i.e. the combined The gain of the system antenna(s) used for the SARA nnector, cable losses and radiating element gain) must not exceed the value transmission line, co specified in the FCC Grant for mobile and fixed or mobile operating configurations: R404M modules: - SARA  o - 13 band 13 dBi in 750 MHz, i.e. LTE FDD R410M -  - 01B modules: SARA o 3.67 dBi in 700 MHz, i.e. LTE FDD - 12 band 5 band o 4.10 dBi in 850 MHz, i.e. LTE FDD - o 6.74 dBi in 1700 MHz, i.e. LTE FDD - 4 band 7.12 dBi in 1900 MHz, i.e. LTE FDD - 2 band o - modules: 02B N410  SARA - R410M - 02B , SARA - R410M - 52B and SARA - o 12 band - 3.66 dBi in 700 MHz, i.e. LTE FDD o 3 .94 dBi in 750 MHz, i.e. LTE FDD - 13 band o 4.41 dBi in 850 MHz, i.e. LTE FDD - 5 band o 6.75 dBi in 1700 MHz, i.e. LTE FDD - 4 band o 2 band 7.00 dBi in 1900 MHz, i.e. LTE FDD -  SARA - R412M - 02B modules: 8.69 dBi in 700 MHz, i.e. LTE FDD - 12 band o - o 9.15 dBi in 750 MHz, i.e . LTE FDD 13 band - 9.41 o 5 band GSM 850 / dBi in 850 MHz, i.e. LTE FDD 4 band - dBi in 1700 MHz, i.e. LTE FDD 12.01 o o 2 band - LTE FDD GSM 1900 / dBi in 1900 MHz, i.e. 12.01 Approvals 16029218 - R11 - UBX Page 97 of 116

98 SARA - System Integration Manual - R4/N4 series 4.2.3 Modifications made to this device that The FCC requires the user to be notified that any changes or modifications are not expressly approved by u - blox could void the user's authority to operate the equipment. R4/N4 series - SARA Manufacturers of mobile or fixed devices incorporating the ⚠ modules are modules for their own final products authorized to use the FCC Grants of the SARA - R4/N4 series according to the conditions referenced in the certificates. the outside, or the host device shall bear a The FCC Label shall in the above case be visible from ⚠ second label stating: - o For SARA R404M modules: "Contains FCC ID: XPY2AGQN1NNN" "Contains FCC ID: XPY2AGQN4NNN" N410 - modules : o For SARA - R410M and SARA R412M cellular modules: "Contains FCC ID: XP YUBX18ZO01" - For SARA o R4/N4 series - SARA IMPORTANT: Manufacturers of portable applications incorporating the ⚠ modules are required to have their final product certified and apply for their own FCC Grant related ble device. This is mandatory to meet the SAR requirements for portable to the specific porta devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. 15.105 this equipment has been tested and found to comply with the Additional Note: as per 47CFR ⚠ limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed ion. This to provide reasonable protection against harmful interference in a residential installat equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. occur in a particular installation. If this However, there is no guarantee that interference will not equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more o f the following measures: Reorient or relocate the receiving antenna o Increase the separation between the equipment and receiver o Connect the equipment into an outlet on a circuit different from that to which the receiver is o connected o Consultant the dealer o r an experienced radio/TV technician for help Innovation, Science 4.3 Economic Development Canada notice , ISED Canada (formerly known as IC - Industry Canada) Certification Numbers: u - blox SARA 2AGQN4NNN  - 8595A - R410M and SARA - N410 cellular modules: - blox SARA - u  UBX18ZO01 - 8595A R412M cellular modules: Declaration of Conformity 4.3.1 exempt RSS standard(s). Operation is subject to This device complies with the ISED Canada license - the following two conditions:  this device may not cause harmful interference this devic  e must accept any interference received, including interference that may cause undesired operation Approvals 16029218 - R11 - UBX Page 98 of 116

99 - SARA System Integration Manual - R4/N4 series Radiofrequency radiation exposure information: this equipment complies with the radiation ⚠ exposure limits prescribed for an uncontrolled environment for fixe d and mobile use conditions. This equipment should be installed and operated with a minimum distance of 20 cm between the located or radiator and the body of the user or nearby persons. This transmitter must not be co - operating in conjunction with any othe r antenna or transmitter except as authorized in the certification of the product. The gain of the system antenna(s) used for the modules (i.e. the combined R - SARA ⚠ 4/N4 series and radiating element gain) must not exceed the value transmission line, connector, cable losses stated in the ISED Canada Grant for mobile and fixed or mobile operating configurations: - SARA  01B modules: - R410M 3.67 dBi in 700 MHz, i.e. LTE FDD - 12 band o o 4.10 dBi in 850 MHz, i.e. LTE FDD - 5 band dBi in 1700 MHz, i.e. LTE FDD o 6.74 4 band - o 2 band - 7.12 dBi in 1900 MHz, i.e. LTE FDD SARA 52B - N410 - 02B modules:  and SARA - R410M - 02B , SARA - R410M - 3.66 dBi in 700 MHz, i.e. LTE FDD o 12 band - o 3.94 dBi in 750 MHz, i.e. LTE FDD - 13 band 4.41 dBi in 850 MHz, i.e. LTE FDD o - 5 band 4 band - 6.75 dBi in 1700 MHz, i.e. LTE FDD o 7.00 dBi in 1900 MHz, i.e. LTE FDD - 2 band o  SARA - R412M - 02B modules: - o 12 band 5.63 dBi in 700 MHz, i.e. LTE FDD o 5.94 dBi in 750 MHz, i.e. LTE FDD - 13 band 6.12 dBi in 850 MHz, i.e. GSM 850 / LTE FDD o - 5 band o 8.29 dB i in 1700 MHz, i.e. LTE FDD - 4 band 2 band 8.52 dBi in 1900 MHz, i.e. GSM 1900 / LTE FDD - o Modifications 4.3.2 ISED Canada requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u - blox could void t he user's authority to operate the equipment. ⚠ modules are R4/N4 series - SARA Manufacturers of mobile or fixed devices incorporating the SARA - R4/N4 series modules for their own authorized to use the ISED Canada Certificates of the final products according to the conditions referenced in the certificates. ⚠ The ISED Canada Label shall in the above case be visible from the outside, or the host device shall bear a second label stating: 2AGQN4NNN" - "Contains IC: 8595A modules: N410 - - and SARA R410M o For SARA : - R412M cellular modules: "Contains IC 8595A - UBX18ZO01" o For SARA ⚠ Innovation, Science and Economic Development Canada (ISED) Notices This Class B digital appara tus complies with Canadian CAN ICES - 3(B) / NMB - 3(B). Operation is subject to the following two conditions:  this device may not cause interference  this device must accept any interference, including interference that may cause undesired operation of the dev ice Approvals 16029218 - R11 - UBX Page 99 of 116

100 - SARA - System Integration Manual R4/N4 series Radio Frequency (RF) Exposure Information blox Cellular Module is below the Innovation, Science and - The radiated output power of the u Economic Development Canada (ISED) radio frequency exposure limits. The u blox Cellular Module - nner such that the potential for human contact during normal operation is should be used in a ma minimized. This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions (antennas are greater than 20 cm from a person's body). This device has been certified for use in Canada. Status of the listing in the Industry Canada’s REL (Radio Equipment List) can be found at the following web address: http://www. ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=eng Additional Canadian information on RF exposure also can be found at the following web address: gst http://www.ic.gc.ca/eic/site/smt .nsf/eng/sf08792.html - ⚠ IMPORTANT: Manufacturers of portable applications incorporating the SARA - R4/N4 series modules are required to have their final product certified and apply for their own Industry Canada elated to the specific portable device. This is mandatory to meet the SAR Certificate r requirements for portable devices. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. Avis d'Innovation, Sciences et Développement économique Canada (ISDE) ⚠ 3(B) / Cet appareil numérique de classe B est conforme aux normes canadiennes CAN ICES - 3(B). - NMB Son fonctionnement est soumis aux deux conditions suivantes: ser d'interférence cet appareil ne doit pas cau o cet appareil doit accepter toute interférence, notamment les interférences qui peuvent o affecter son fonctionnement Informations concernant l'exposition aux fréquences radio (RF) lox Cellular Module est inférieure à la - fil u - b La puissance de sortie émise par l’appareil de sans limite d'exposition aux fréquences radio d'Innovation, Sciences et Développement économique Canada (ISDE). Utilisez l’appareil de sans - fil u - blox Cellular Module de façon à minimiser les contacts humains lors du fonc tionnement normal. Ce périphérique a été évalué et démontré conforme aux limites d'exposition aux fréquences radio (RF) d'IC lorsqu'il est installé dans des produits hôtes particuliers qui fonctionnent dans des es (les antennes se situent à plus de 20 centimètres conditions d'exposition à des appareils mobil du corps d'une personne). Ce périphérique est homologué pour l'utilisation au Canada. Pour consulter l'entrée correspondant - à l’appareil dans la liste d'équipement radio (REL Radio Equipment List) d'In dustrie Canada - vous sur: rendez http://www.ic.gc.ca/app/sitt/reltel/srch/nwRdSrch.do?lang=fra Pour des informations supplémentaires concernant l'exposition aux RF au Canada rend ez - vous gst.nsf/fra/sf08792.html http://www.ic.gc.ca/eic/site/smt sur: - ⚠ IMPORTANT: les fabricants d'applications portables contenant les modules de la SARA - R4/N4 doivent faire certifier leur produit final et déposer directement leur candidature pour une series certification FCC ainsi que pour un certificat ISDE Canada délivré par l'organisme chargé de ce type e afin d'être en accord avec les exigences SAR pour les d'appareil portable. Ceci est obligatoir appareils portables. Tout changement ou modification non expressément approuvé par la partie responsable de la certification peut annuler le droit d'utiliser l'équipement. Approvals 16029218 - R11 - UBX Page 100 of 116

101 R4/N4 series SARA System Integration Manual - - 4.4 European Conformance CE mark s module product version SARA - R412M - and SARA 02B - R410M - been evaluated against the have 02B essential requirements of the Radio Equipment Directive 2014/53/EU. with In order to satisfy the essential requirements of the 2014/53/EU RED, the modules are compliant the following standards:  Radio Spectrum Efficiency (Article 3.2): o - 1 EN 301 908 o EN 301 908 13 - EN 301 511 o Electromagnetic Compatibility (Article 3.1b):  1 - o EN 301 489 52 - EN 301 489 o  Health and Safety (Article 3.1a) - EN 62368 o 1 o EN 62311 Radiofrequency ⚠ radiation exposure Information: this equipment complies with radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions. This cm between equipment should be installed and operated with a minimum distance of 20 the radiator and the body of the user or nearby persons. This transmitter must not be co - located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product. - - 02B modules ⚠ The gain of the system antenna(s) u sed for the SARA - R410M R412M 02B and SARA - (i.e. the combined transmission line, connector, cable losses and radiating element gain) must not exceed the values stated in the Declaration of Conformity of the modules, for mobile and fixed or mobil e operating configurations: 02B modules: - R410M - SARA  o 20 band - 8.2 dBi in 800 MHz, i.e. LTE FDD - 8.4 dBi in 900 MHz, i.e. LTE FDD 8 band o 11.3 dBi in 1800 MHz, i.e. LTE FDD - o 3 band - R412M SARA  - 02B modules: o 20 band - 8.2 dBi in 800 MHz, i.e. LTE FDD o 8 band - MHz, i.e. GSM 900 / LTE FDD 3.21 dBi in 900 3 band - 9.09 dBi in 1800 MHz, i.e. GSM 1800 / LTE FDD o - the SARA - , 02B modules - R412M R410M and SARA 02B - The conformity assessment procedure for referred to in Article 17 and detailed in Annex II of Directive 2014/53/EU, has b een followed. Thus, the following marking is included in the product: Taiwanese National Communication Commission 4.5 The SARA - R410M - 02B product version has the applicable regulatory approval for Taiwan (NCC) -  R410M - 02B modules NCC ID: CCAA18NB0010T3 SARA CCAA18NB0010T3 Approvals - UBX - R11 16029218 116 of 101 Page

102 SARA - System Integration Ma nual - R4/N4 series 5 Product testing - series production test - blox in 5.1 u - u blox focuses on high quality for its products. All units produced are fully tested automatically on the ve been implemented in the production line. production line. Stringent quality control processes ha Defective units are analyzed in detail to improve production quality. This is achieved with automatic test equipment (ATE) in the production line, which logs all production and measurement data. A detailed test r Figure eport for each unit can be generated from the system. 57 illustrates the typical automatic test equipment (ATE) in a production line. The following typical tests are among the production tests.  verification, IMEI programming) test (firmware download, flash firmware - Digital self Measurement of voltages and currents   Adjustment of ADC measurement interfaces  Functional tests (serial interface communication, SIM card communication)  Digital tests (GPIOs and other interfaces)  Measurement and calibration o f RF characteristics in all supported bands (such as receiver S/N verification, frequency tuning of the reference clock, calibration of transmitter and receiver power levels, etc.)  Verification of the RF characteristics after calibration (i.e. modulation a ccuracy, power levels, spectrum, etc. are checked to ensure they are all within tolerances when calibration parameters are applied) Figure : Automatic test equipment for module tests 57 Product testing 16029218 - R11 - UBX Page 102 of 116

103 SARA - System Integration Manual - R4/N4 series manufacturers Test parameters for OEM 5.2 blox (with 100% coverage), an OEM manufacturer does not need to - Because of the testing done by u repeat the firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test. ver, an OEM manufacturer should focus on: Howe  Module assembly on the device; it should be verified that: o The soldering and handling process did not damage the module components o All module pins are well soldered on the device board o There are no short circuits b etween pins Component assembly on the device; it should be verified that:  o Communication with the host controller can be established The interfaces between the module and device are working o Overall RF performance test of the device including the antenna o Ded icated tests can be implemented to check the device. For example, the measurement of the module current consumption when set in a specified status can detect a short circuit if compared with a “Golden Device” result. used to perform functional tests on the digital interfaces In addition, module AT commands can be (communication with the host controller, check the SIM interface, GPIOs, etc.) or to perform RF for details). 5.2.2 performance tests (see the following section 5.2.1 “Go/No go” tests for integrated devices signal quality with a “Golden Device” in a location A “Go/No go” test is typically used to compare the wn signal quality. This test should be performed after the with excellent network coverage and kno data connection has been established. AT+CSQ is the typical AT command used to check signal R4/N4 series quality in term of RSSI. See the - for detail usage of the AT Commands Manual [2] SARA AT command. These kinds of test may be useful as a “go/no go” test but not for RF performance measurements. ☞ This test is suitable to check the functionality of communications with the host controller, the SIM - card and the power supply. It is also a means to verify if components at the antenna interface are well soldered. RF functional tests 5.2.2 The overall RF functional test of the device including the antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator with the assistance of the AT+UTEST command over the AT command user interface. The AT+UTE ST command provides a simple interface to set the module to Rx or Tx test modes ignoring the LTE signaling protocol. The command can set the module into: transmitting mode in a specified channel and power level in all supported bands   receiving mode in a sp ecified channel to return the measured power level in all supported bands ☞ - for the AT+UTEST command syntax SARA R4/N4 series AT Commands Manual [2] See the description and detail guide of usage. Product testing 16029218 - R11 - UBX Page 103 of 116

104 SARA - System Integration Manual - R4/N4 series This feature allows the measurement of the transmitter and receiver power levels to check the ule antenna interface and to check other device interfaces component assembly related to the mod on which the RF performance depends. ⚠ To avoid module damage during a transmitter test, a suitable antenna according to module specifications or a 50 termination must be connected to the ANT port.  ⚠ To avoid module damage during a receiver test, the maximum power level received at the ANT port must meet module specifications. ☞ The AT+UTEST command sets the module to emit RF power ignoring LTE signaling protocol. This emission can generate interferenc e that can be prohibited by law in some countries. The use of this feature is intended for testing purposes in controlled environments by qualified users and must not be used during the normal module operation. Follow the instructions suggested in the - u blox assumes no responsibilities for the inappropriate use of this feature. - ox documentation. u bl Figure 58 illustrates a typical test setup for such an RF functional test. Wideband Cellular antenna antenna Application SARA - R4/N4 Processor Spectrum AT Analyzer commands IN ANT or TX Power Meter Application Board Cellular Wideband antenna antenna Application SARA R4/N4 - Processor AT commands Signal ANT OUT RX Generator Application Board SARA : Setup with spectrum analyzer or power meter and signal generator for 58 Figure measurements RF R4/N4 series - Product testing 16029218 - R11 - UBX Page 104 of 116

105 SARA - System Integration Manual - R4/N4 series Appendix A Migration between SARA modules A.1 Overview SARA - G3 2G modules, SARA - U2 3G / 2G modules, SARA - R4 /N4 LTE Cat M1/NB1 / 2G modules and SARA N2 LTE Cat NB1 modules have exactly the same u - blox SARA form factor (26.0 x 16.0 mm, LGA - 96 - pin), with compatible pin assignments, as in Figure 59 . Any one of the modules can be mounted on a single application board using exactly the same copper mask, solder mask and paste mask. GND GND GND GND GND GND GND GND GND GND GND GND ANT_DET ANT ANT ANT_DET GND GND GND GND GND GND GND GND GND GND ANT_DET GND GND GND ANT GND GND GND GND GND GND GND GND GND GND GND ANT_DET ANT 59 58 61 63 64 57 57 55 54 58 55 54 57 55 63 61 58 56 60 61 63 62 60 59 62 56 64 60 54 55 57 56 62 59 58 60 64 61 63 59 62 56 64 54 53 53 53 53 1 1 1 1 GND VCC GND VCC GND VCC GND VCC 68 69 70 69 66 65 70 69 68 67 70 66 65 67 68 66 70 69 68 67 66 65 67 65 52 2 2 52 52 52 2 2 VCC V_BCKP RSVD VCC RSVD VCC V_BCKP VCC 3 3 3 51 51 3 51 51 VCC VCC VCC GND VCC GND GND GND 71 73 71 72 72 73 74 71 75 76 76 76 75 76 75 74 73 72 75 72 74 74 73 71 4 50 4 4 4 50 50 50 GND V_INT GND GND GND V_INT V_INT V_INT 78 77 78 77 78 77 77 78 49 49 49 5 5 49 5 5 MIC_P GND GND GND GND RSVD SDIO_D1 RSVD 6 6 6 6 48 48 48 48 RSVD MIC_N DSR DSR RSVD DSR SDIO_D3 RSVD 7 7 7 47 47 47 47 7 RSVD RI MIC_GND RSVD RI RSVD RI SDIO_D0 8 8 46 46 46 46 8 8 RSVD DCD DCD MIC_BIAS SDIO_CMD RSVD DCD RSVD 79 79 80 80 80 80 79 79 9 9 9 9 45 45 45 45 SDIO_CLK DTR DTR RSVD SPK_N RSVD DTR RSVD 10 10 44 44 10 44 10 44 RTS RTS RSVD RSVD SPK_P SDIO_D2 RTS RTS G3 U2 N2 - SARA - R4/N4 - - SARA SARA SARA 43 43 11 11 11 43 43 11 CTS GND CTS CTS CTS GND GND GND 12 42 12 12 42 42 42 12 TXD RSVD TXD SIM_DET SIM_DET GPIO5 TXD TXD Top View Top View Top View Top View 13 13 41 41 13 41 41 13 RXD VSIM VSIM RXD VSIM VSIM RXD RXD 82 81 81 82 81 82 81 82 40 14 14 40 40 14 40 14 GND SIM_RST GND GND SIM_RST SIM_RST SIM_RST GND 39 39 39 15 15 15 15 39 RSVD SIM_IO SIM_IO PWR_ON PWR_ON PWR_ON SIM_IO SIM_IO 38 38 16 38 16 16 16 38 GPIO1 SIM_CLK GPIO1 SIM_CLK SIM_CLK GPIO1 GPIO1 SIM_CLK 17 17 17 17 37 37 37 37 I2S_RXD/SPI_MISO VUSB_DET RSVD RSVD I2S_RXD RSVD VUSB_DET I2S_RXD 84 83 83 84 84 83 84 83 96: GND 96: GND - 96: GND - - Pin 65 Pin 65 - 96: GND Pin 65 Pin 65 18 36 36 18 36 18 18 36 I2S_CLK I2S_CLK RESET_N RESET_N I2S_CLK/SPI_CLK RESET_N RSVD RESET_N 86 86 90 88 89 88 87 85 86 85 85 90 87 87 88 89 89 90 90 89 88 85 87 86 35 35 35 19 19 19 35 19 I2S_TXD RSVD RSVD RSVD I2S_TXD CODEC_CLK I2S_TXD/SPI_CS GPIO6 20 20 20 20 34 34 34 34 I2S_WA GND GND RSVD I2S_WA/SPI_MOSI GND GND I2S_WA 94 91 95 94 92 95 96 93 92 92 91 91 93 91 92 93 94 95 96 93 96 94 96 95 21 33 33 21 21 33 21 33 GND RSVD RSVD GND RSVD GND RSVD GND 23 25 22 23 25 26 28 29 31 32 26 24 27 30 28 29 31 32 24 24 27 30 27 22 23 25 26 28 29 30 32 31 22 23 25 26 28 29 31 24 27 30 32 22 - - SCL SCL SCL SCL SDA SDA SDA SDA GND GND GND GND GND GND GND GND GND GND GND GND RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD GPIO2 GPIO2 GPIO2 GPIO2 GPIO4 GPIO4 GPIO3 GPIO4 GPIO3 GPIO3 USB_D USB_D USB_D+ USB_D+ TXD_AUX RXD_AUX : SARA - G3, SARA - U2, SARA - R4 /N4 Figure and SARA - N2 modules’ layout and pin assignment 59 summarizes the interfaces provided by the SARA - G3, SARA - 39 - R4/N4, SARA - N2 Table U2, SARA ules. mod Modules RAT Power System SIM Serial Audio Other indication on input off input C) - - 2 Reset input SDIO USB DDC (I SPI UART AUX UART Analog audio Digital audio SIM detection 13/26 MHz output SIM interface GPIOs Module supply input Network Switch Switch Antenna detection 1.8 V supply Output GNSS via modem RTC supply I/O SARA - G3 2G • • • • • • • • • • • • • • • • U2 3G, 2G - SARA • • • • • • • • • • • • • • • • • • SARA - R4/N4 LTE M1 / NB1, 2G • • • • • • • • • • • • • • □ □ □ □ SARA - N2 LTE NB1 • • • • • • • • ● = supported by future product versions = supported by available product version □ R4 Table N2 - SARA and /N4 modules interfaces - U2, SARA - G3, SARA - : Summary of SARA 39 Page - 16029218 116 of 105 - Appendix R11 UBX

106 SARA - System Integration Manual - R4/N4 series SARA modules are also form - factor compatible with the blox LISA, LARA and TOBY cellular module - u families: although each has a different form factor, the footprints for the TOBY, LISA, SARA and LARA modules have been developed to ensure layout compatibility. With the u LISA, SARA or LARA module can be alternatively blox “nested design” solution, any TOBY, - . 60 Figure mounted on the same space of a single “nested” application board as described in - blox reference nested for implementing a nested application board, a description of the u Guidelines design and a comparison between the TOBY, LISA, SARA and LARA modules are provided in the . [21] Nested Design Application Note TOBY cellular module module LISA cellular module LARA cellular SARA cellular module Nested application board 60 Figure lodged on the same nested footprint : TOBY, LISA, SARA, LARA modules’ layout compatibility: all modules Appendix - 16029218 - R11 UBX Page 106 of 116

107 SARA R4/N4 series - System Integration Manual - Pin A.2 - out comparison R4 shows a pin out comparison between the SARA - G3, SARA U2, SARA - - /N4 , and SARA - N2 modules. 40 Table - - G3 SARA - U2 No SARA - R4 SARA - N2 SARA Pin Name Pin Name Description Description Pin Name Description Pin Name Description Remarks for migration 1 GND Ground GND Ground Ground GND Ground GND 2 V_BCKP RTC Supply I/O V_BCKP RTC supply vs Reserved RTC Supply I/O RSVD Reserved RSVD Reserved Ground GND Ground GND Ground GND Ground GND 3 V_INT is switched off in deep V_INT Interfaces Supply Output: 4 Interfaces Supply Output: V_INT Interfaces Supply Output: V_INT Interfaces Supply Output: V_INT sleep (R4), or if radio is off 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max 1.8 V typ, 70 mA max (N2) . TestPoint always Switched - off if radio is off off in deep - sleep Switched - recommended 5 GND Ground GND Ground GND Ground GND Ground DSR UART DSR Output DSR 6 Not supported by N2 Reserved RSVD UART DSR Output DSR UART DSR Output V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse driver strength strength: 6 mA Driver strength: 2 mA Driver strength: 1 mA Driver RI UART RI Output Not supported by N2 Reserved 7 RSVD RI UART RI Output UART RI Output RI V_INT level (1.8 V) V_INT level (1.8 V) (1.8 V) V_INT level Diverse driver strength Driver strength: 2 mA Driver strength: 6 mA Driver strength: 2 mA DCD UART DCD Output Not supported by N2 8 DCD UART DCD Output Reserved DCD UART DCD Output RSVD V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse driver strength Driver strength: 2 mA Driver strength: 2 mA Driver strength: 6 mA Reserved RSVD UART DTR Input Not supported by N2 UART DTR Input DTR 9 UART DTR Input DTR DTR V_INT level (1.8 V) V_INT level (1.8 V) Diverse internal pull V_INT level (1.8 V) up value - - up: ~33 k Internal pull - Internal pull - up: ~14 k up: ~100 k Internal pull It must be set low to have It must be set low to have It must be set low to have greeting text sent over sent over greeting text URCs sent over UART UART UART 21 21 ; Diverse level (V_INT vs VCC) UART RTS Input 10 RTS UART RTS Input UART RTS Input RTS UART RTS Input RTS RTS Diverse internal pull up value; - V_INT level (1.8 VCC level (3.6 V typ.) V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse functions supported. - Internal pull up: ~78 k Internal pull - Internal pull - up: ~100 k Internal pull - up: ~8 k up:~58 k It must be set low to use UART on ‘00’, ‘01’ product versions 21 R410M - N2 modules - 02B product versions and SARA - Not supported by “00”, “01”, SARA 16029218 - R11 Appendix - UBX Page 107 of 116

108 SARA System Integration Manual - R4/N4 series - No SARA - G3 N2 - SARA SARA - U2 R4 - SARA Pin Name Pin Name Pin Name Description Description Pin Name Description Remarks for migration Description 21 21 UART CTS Output 11 CTS Diverse level (V_INT vs VCC) UART CTS Output CTS UART CTS Output CTS CTS UART CTS Output V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Diverse driver strength. VCC level (3.6 V typ.) Driver strength: 6 mA D river strength: 2 mA Diverse functions supported. Driver strength: 6 mA Driver strength: 1 mA Configurable as Ring Indicator or Network Indicator Diverse level (V_INT vs VCC) ; TXD UART Data Input 12 TXD UART Data Input TXD UART Data Input TXD UART Data Input ; down - up / pull - Diverse pull V_INT level (1.8 V) VCC level (3.6 V typ.) V_INT level (1.8 V) V_INT level (1.8 V) TestPoint always up: ~8 k Internal pull - up:~18 k - pull Internal pull - up/ - down: ~100k - down - Internal pull up/ No internal recommended ; Diverse level (V_INT vs VCC) 13 UART Data Output RXD UART Data Output UART Data Output RXD UART Data Output RXD RXD Diverse driver strength ; V_INT level (1.8 V) VCC level (3.6 V typ.) V_INT level (1.8 V) V_INT level (1.8 V) TestPoint always Driver strength: 1 mA Driver strength: 6 mA Driver strength: 2 mA Driver strength: 6 mA recommended Ground GND Ground Ground GND GND 14 GND Ground Not supported by N2 ; Internal RSVD PWR_ON Power PWR_ON on Input - 15 Reserved PWR_ON Power - on Input on Input - Power ; Diverse up - vs No internal pull No internal pull - up up - up - 200 k internal pull No internal pull s; Diverse timing voltage levels; L - 0.30 V ÷ 0.65 V - level: - L - 0.10 V ÷ 0.65 V 0.30 V ÷ 0.35 V - level: - L level: Diverse functions supported; H - level: 1.50 V ÷ 4.40 V level: 2.00 V ÷ 4.50 V - H H - level: 1.17 V ÷ 2.10 V TestPoint recommended for level pulse time: ON L level time: level pulse time: - ON L - ON L - R4 3.2 s max s max μ s min / 80 μ 50 5 ms min – 0.15 s min OFF L - OFF L - level pulse time: OFF L - level pulse time: level pulse time: 1.5 s m in Not Available 1 s min GPIO (G340/G350) GPIO GPIO1 / RSVD 16 GPIO Diverse driver strength GPIO1 GPIO1 GPIO GPIO1 Reserved (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) TestPoint recommended for N2 V_INT level (1.8 V) Default: Pin disabled Default: Pin disabled Configurable as secondary Default: Pin disabled UART data output: Driver strength: 2 mA Driver strength: 6 mA TestPoint recommended for Driver strength: 6 mA diagnostic USB detection vs Reserved; RSVD 5 V, USB Supply Detect Input VUSB_DET 5 V, USB Supply Detect Input VUSB_DET Reserved RSVD 17 Reserved TestPoint recommended for U2/R4 Abrupt shutdown/reset in Abrupt shutdown input up - Diverse internal pull RESET_N put RESET_N Reset input RESET_N Reset input 18 RESET_N Internal - up 78 k internal pull - up up - diode & pull 37 k internal pull Diverse voltage levels. - internal pull  10 k up - 0.30 V ÷ 0.30 V Diverse timings. 0.30 V ÷ 0.36*VCC - level: L 0.30 V ÷ 0.35 V - level: - L - L - level: 0.30 V ÷ 0.51 V level: - L - Diverse functions supported. CC ÷ VCC - H H - level: 2.00 V ÷ 4.70 V level: 0.52*V level: 1.17 V ÷ 2.10 V - H - level: 1.32 V ÷ 2.01 V H level pulse time: Reset L - level pulse time: level pulse time: TestPoint always Reset L OFF L - - Reset L - level pulse time: recommended 500 ns min 10 s min 50 ms min (G340/G350) 50 ms min 3 s min (G300/G310) - UBX 116 of - 16029218 108 Page Appendix R11

109 SARA - System I ntegration Manual - R4/N4 series No SARA - G3 N2 SARA - U2 - SARA SARA - R4 Pin Name Description Description Pin Name Description Description Pin Name Remarks for migration Pin Name 19 RSVD Reserved CODEC_CLK 13 or 26 MHz Output Clock / GPIO vs Reserved Reserved RSVD GPIO GPIO6 V_INT level (1.8 V) V_INT level (1.8 V) Default: Pin disabled disabled Default: Pin Driver strength: 4 mA Driver strength: 2 mA Ground GND Ground Ground GND Ground GND 20 GND GND 21 Ground GND Ground GND Ground GND Ground 22 GND Ground GND Ground GND Ground GND Ground GPIO (G340/G350) 23 GPIO vs Reserved GPIO2 / RSVD Reserved RSVD GPIO GPIO2 GPIO2 GPIO Reserved (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS supply enable Default: Pin disabled Default: GNSS supply enable Driver strength: 2 mA Driver strength: 1 mA Driver strength: 6 mA 23 GPIO3 / GPIO (G340/G350) IO GPIO3 GPIO2 GPIO GPIO3 24 GP Diverse driver strength GPIO 32K_OUT 32 kHz Output (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS data ready Default: Pin disabled ed Default: Pin disabl Default: GNSS data ready Driver strength: 2 mA Driver strength: 1 mA Driver strength: 6 mA Driver strength: 5 mA GPIO (G340/G350) GPIO GPIO vs Reserved GPIO4 GPIO GPIO4 Reserved RSVD GPIO4 / RSVD 25 Reserved (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Default: GNSS RTC sharing Default: Output/Low Default: GNSS RTC sharing Driver strength: 6 mA Driver strength: 2 mA Driver strength: 6 mA 2 23 2 22 2 2 I SDA / C Data I/O (G340/G350) I C Data Internal vs No internal pull - up 26 I/O SDA I I C Data I/O SDA SDA / C Data I/O Reserved (G300/G310) RSVD V_INT level (1.8 V) V_INT level (1.8 V) ‘04’ version) AUX UART in ( V_INT level (1.8 V) V_INT level (1.8 V) Open drain Open drain Open drain Open drain No internal pull - Internal 2.2 k pull - up up - up No internal pull No internal pull up - 2 2 22 23 2 2 I SCL / C Clock Out (G340/G350) I Internal vs No internal pull 27 C Clock Output I SCL / SCL C Clock Output up Output C Clock - I SCL RSVD Reserved (G300/G310) V_INT level (1.8 V) (‘04’ version) V_INT level (1.8 V) AUX UART out V_INT level (1.8 V) Open drain Open drain V_INT level (1.8 V) Open drain up No internal pull - up Open drain Internal 2.2 k pull - up - No internal pull - up No internal pull 28 ) - USB Data I/O (D - USB_D USB / AUX UART vs Reserved Reserved RXD_AUX Aux UART Data Out USB_D - USB Data I/O (D - ) RSVD - TestPoint recommended for High Speed USB 2.0 - Speed USB 2.0 High V_INT level (1.8 V) SARA - G3/U2/R4 modules 22 Not supported by “00” and “01” product versions 23 Not supported by “02” product versions 16029218 - R11 Appendix - UBX Page 109 of 116

110 SARA System Integration Manual - R4/N4 series - SARA - G3 SARA U2 SARA - R4 SARA - N2 No - Description Pin Name Pin Name Description Description Pin Name Pin Name Description Remarks for migration 29 TXD_AUX Aux UART Data In USB / AUX UART vs Reserved USB_D+ USB Data I/O (D+) Reserved RSVD USB_D+ USB Data I/O (D+) - Speed USB 2.0 Speed USB 2.0 - High High V_INT level (1.8 V) TestPoint recommended for SARA - G3/U2/R4 modules GND Ground GND Ground GND Ground 30 GND Ground RSVD / Reserved (G340/G350) Reserved Reserved 32 kHz Input vs Reserved 31 RSVD RSVD Reserved RSVD 32 kHz Input (G300/G310) EXT32K 32 GND Ground GND Ground GND Ground GND Ground It can be RSVD 33 It can be connected to GND RSVD connected to GND RSVD It must be connected to GND RSVD It must be connected to GND 24 2 2 2 S Word / SPI Alignm I I2S_WA / S Word Align.(G340/G350) I I2S_WA / I2S_WA RSVD Reserved I2S vs SPI vs Reserved 34 I S Word Alignment 24 SPI_MOSI RSVD Reserved (G300/G310) MOSI V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Driver strength: 2 mA Driver strength: 6 mA Driver strength: 2 mA 2 24 2 2 I2S_TXD / I I2S_TXD / / SPI chip S Data Output S Data Out I I2S vs SPI vs Reserved Reserved I2S_TXD 35 I S Data Output RSVD 24 (G340/G350) Reserved select RSVD SPI_CS V_INT level (1.8 V) (G300/G310) V_INT level (1.8 V) Driver strength: 2 mA V_INT level (1.8 V) Driver strength: 2 mA Driver strength: 5 mA 2 24 24 2 2 I2S_CLK / S Clock (G340/G350) I I2S_CLK / RSVD I2S_CLK I S Clock I2S vs SPI vs Reserved Reserved I S Clock / SPI clock 36 Reserved (G300/G310) RSVD SPI_CLK V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Driver strength: 2 mA Driver strength: 2 mA Driver strength: 5 mA 2 2 24 24 2 I I2S_RXD / S Data Input (G340/G350) I2S_RXD / Reserved RSVD I2S_RXD I S Data Input 37 / SPI MISO I I2S vs SPI vs Reserved S Data Input RSVD SPI_MISO Reserved (G300/G310) V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) 1.8V/3V SIM Clock Output 1.8V SIM Clock Output SIM_CLK SIM_CLK 38 SIM_CLK 1.8V/3V SIM Clock Output SIM_CLK 1.8V/3V SIM Clock Output SIM_IO SIM_IO 1.8V/3V SIM Data I/O 1.8V SIM Data I/O 39 SIM_IO 1.8V/3V SIM Data I/O 1.8V/3V SIM Data I/O SIM_IO up up Internal 4.7 k pull Internal 4.7 k pull - up - - Internal 4.7 k pull Internal 4.7 k pull - up 40 SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V/3V SIM Reset Output SIM_RST 1.8V SIM Reset Output 41 VSIM 1.8V/3V SIM Supply 1.8V SIM Supply Output Output VSIM 1.8V/3V SIM Supply Output VSIM 1.8V/3V SIM Supply Output VSIM RSVD SIM_DET SIM Detection Input SIM Detection vs Reserved SIM_DET SIM Detection Input 42 Reserved GPIO5 SIM Detection Input V_INT level (1.8 V) V_INT level (1.8 V) V_INT level (1.8 V) Ground 43 GND Ground GND Ground GND Ground GND 24 SPK_P / Analog Audio Out (+) / SDIO_D2 44 SDIO serial data [2] RSVD Reserved Analog Audio vs SDIO vs RSVD Reserved RSVD RSVD Reserved 24 Not supported by “00”, “01” and “x2” product version 16029218 - R11 Appendix - UBX Page 110 of 116

111 SARA System Integration Manual - R4/N4 series - SARA - G3 SARA SARA - U2 N2 - SARA No - R4 Description Pin Name Description Description Pin Name Pin Name Description Remarks for migration Pin Name 24 Analog Audio Out ( - ) / SPK_N / 45 Reserved RSVD Reserved SDIO_CLK SDIO serial clock Analog Audio vs SDIO vs RSVD RSVD RSVD Reserved 24 MIC_BIAS / Microphone Supply Out / Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_CMD SDIO command 46 RSVD Reserved Reserved RSVD 24 MIC_GND / Microphone Ground / 47 Analog Audio vs SDIO vs RSVD Reserved RSVD Reserved SDIO_D0 SDIO serial data [0] RSVD Reserved RSVD 24 MIC_N / ) / Analog Audio In ( - RSVD Analog Audio vs SDIO vs RSVD Reserved RSVD Reserved 48 SDIO serial data [3] SDIO_D3 RSVD Reserved 24 Analog Audio In (+) / 49 Analog Audio vs SDIO vs RSVD RSVD Reserved SDIO_D1 SDIO serial data [1] RSVD MIC_P / RSVD Reserved Reserved 50 GND Ground GND GND Ground GND Ground Ground Module Supply Input VCC VCC Diverse voltage levels. Modul e Supply Input Module Supply Input VCC 51 - 53 VCC Module Supply Input Diverse current consumption. Normal op. range: Normal op. range: Normal op. range: Normal op. range: 3.1 V – 4.0 V 4.2 V – 3.2 V – 3.3 V – 4.4 V 4.5 V 3.35 V external ecommended R capacitors and other parts Extended op. range: Extended op. range: Extended op. range: for Extended op. range: – 4.5 V EMI suppression may differ . 4.2 V 3.1 V 3.0 V – 4.3 V 4.5 V – 3.00 V – 2.75 V Current consumption: . Regular pF / nF recommended Current consumption: Current consumption: Current consumption: ~2.0A pulse current in 2G ~2.0A pulse current in 2G pulse current LTE ~0.3A ~2.0A pulse current in 2G Diverse functions supported. 100uF) ≥ (recommended 100uF) ≥ (recommended VCC Switch on applying - Switch on applying VCC - ~0.5A LTE pulse current Switch - on applying VCC ≥ (recommended 10uF) - turn No on applying VCC 54 - 55 GND Ground GND Ground GND Ground GND Ground ANT RF Antenna I/O ANT RF Antenna I/O 56 ANT RF Antenna I/O ANT RF Antenna I/O Diverse bands supported GND GND Ground GND Ground Ground GND 61 - 57 Ground 25 Detection vs ANT_DET / Antenna Detection Input / Antenna Antenna Detection Input 62 Antenna Detection Input ANT_DET Antenna Detection Input ANT_DET ANT_DET RSVD Reserved Reserved GND Ground GND Ground GND Ground 96 Ground GND 63 - R4 U2, SARA N2 series modules pin assignments with remarks for migration - and SARA Table 40 : SARA - G3, SARA - - /N4 - R4 /N4 ☞ U2, SARA For further details regarding the characteristics, capabilities, usage or settings applicable for each interface of the SARA - G3, SARA - and SARA [16] N2 series cellular modules, see the related Data Sheet [17] , [18] , the related System Integration Manual [19] , [20] , and the Nested , , - [1] . [21] Design Application Note 25 Not supported by “02” product version Page - 16029218 - 116 of 111 Appendix R11 UBX

112 SARA - System Integration Manual - R4/N4 series Glossary B Definition Abbreviation 2nd Generation Cellular Technology (GSM, GPRS, EGPRS) 2G 3rd Generation Cellular Technology (UMTS, HSDPA, HSUPA) 3G 3rd Generation Partnership Project 3GPP PSK - 8 Shift Keying modulation - 8 Phase Analog to Digital Converter ADC AT Command Interpreter Software Subsystem, or attention AT Cat Category CE European Conformity Direct Current DC DCE Data Communication Equipment DDC Display Data Channel interface DL Link (Reception) - Down Data Terminal Equipment DTE Enhanced Data rates for GSM Evolution (EGPRS) EDGE Extended Discontinuous Reception eDRX EGPRS Enhanced General Packet Radio Service (EDGE) Magnetic Compatibility EMC Electro - Magnetic Interference - Electro EMI Static Discharge Electro - ESD ESR Equivalent Series Resistance E UTRA Evolved Universal Terrestrial Radio Access - Federal Communications Commission FCC United States Frequency Division Duplex FDD Firmware Over AT commands FOAT Firmware Over The Air FOTA File Transfer Protocol FTP FW Firmware GCF Global Certification Forum Shift Keying modulation Gaussian Minimum GMSK - GND Ground Navigation Satellite System GNSS Global GPIO General Purpose Input Output General Packet Radio Service GPRS GPS Global Positioning System Human Body Model HBM HTTP HyperText Transfer Protocol Hardware HW Federal Telecommunications Institute Mexico IFT 2 - Inter C I Integrated Circuit interface 2 S I Inter IC Sound interface ISED Innovation, Science and Economic Development Canada LDO Dropout Low - LGA Land Grid Array Appendix 16029218 - R11 - UBX Page 112 of 116

113 SARA - System Integration Manual - R4/N4 series Definition Abbreviation Low Noise Amplifier LNA Low Power Wide Area LPWA LTE Long Term Evolution Open Mobile Alliance Lightweight Machine Machine protocol - to LWM2M - Machine - to - Machine M2M MQTT Message Queuing Telemetry Transport N/A Not Applicable NAS Non Access Stratum - device: an application device integrating a u Original Equipment Manufacturer OEM blox cellular module Over The Air OTA PA Power Amplifier Pulse Code Modulation PCM Product Change Notification / Sample Delivery Note / Information Note PCN Pulse Frequency Modulation PFM Power Saving Mode PSM PTCRB PCS Type Certification Review Board Pulse Width Modulation PWM Quadrature Phase Shift Keying QPSK Radio Access Technology RAT Radio Frequency RF Radiated Spurious Emission RSE RTC Real Time Clock Surface Acoustic Wave SAW Secure Digital Input Output SDIO Subscriber Identification Module SIM Short Message Service SMS SPI Serial Peripheral Interface Self - Resonant Frequency SRF SSL Secure Socket Layer TBD To Be Defined Transmission Control Protocol TCP TDD Time Division Duplex TDMA Time Division Multiple Access TIS Total Isotropic Sensitivity TP Point - Test Total Radiated Power TRP - Universal Asynchronous Receiver UART Transmitter UDP User Datagram Protocol Universal Integrated Circuit Card UICC UL Link (Transmission) - Up Universal Mobile Telecommunications System UMTS USB Universal Serial Bus VoLTE Voice over LTE VSWR Voltage Standing Wave Ratio abbreviations and terms used Table 41 : Explanation of the Appendix 16029218 - R11 - UBX Page 113 of 116

114 SARA System Integration Manual - R4/N4 series - Related documents u - blox SARA - [1] /N4 series Data Sheet, document number UBX - 16024152 R4 17003787 [2] u - blox SARA - R4 /N4 series AT Commands Manual, document number UBX - - R4 u - blox EVK [3] /N4 User Guide, document number UBX - 16029216 Universal Serial Bus Revision 2.0 specification, [4] http://www.usb.org/developers/docs/usb20_docs/ 2000 [5] ITU - T Recommendation V.24 - 02 - - List of definitions for interchange circuits between Data Terminal Equipment (DTE) and Data Circuit - terminating Equipment (DCE), - http://www.itu.int/rec/T - REC - V.24 200002 - I/en [6] 3GPP TS 27.007 - AT command set for User Equipment (UE) [7] 3GPP TS 27.005 - Us e of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) - Terminal Equipment to User Equipment (TE UE) multiplexer protocol - [8] 3GPP TS 27.010 2 - 9 October 2012 - Rev. 5 - bus specification and user manual - C NXP Semiconductors, I [9] http://www.nxp.com/documents/user_manual/UM1020 4.pdf [10] GSM Association TS.09 - Battery Life Measurement and Current Consumption Technique, https://www.gsma.c om/newsroom/wp - content/uploads/TS.09_v10.1.pdf - [11] 3GPP TS 36.521 - 1 Evolved Universal Terrestrial Radio Access; User Equipment conformance specification; Radio transmission and reception; Part 1: Conformance Testing [12] 3GPP TS 36.521 - 2 - Evolved Universal Terrestrial Radio Access (E - UTRA); User Equipment conformance specification; Radio transmission and reception; Part 2: Implementation ICS) Conformance Statement ( [13] 3GPP TS 36.523 - 2 - Evolved Universal Terrestrial Radio Access (E - UTRA) and Evolved Packet Core (EPC); User Equipment conformance specification; Part 2: Implementation Conformance Statement (ICS) UBX blox End user test Application Note, document number u 13001922 - [14] - - u [15] 14001652 - blox Package Information Guide, document number UBX u - blox SARA - G3 series Data Sheet, document number UBX - 13000993 [16] 13005287 [17] u - blox SARA - U2 series Data Sheet, document number UBX - 15025564 - [18] N2 series Data Sheet, document number UBX u - blox SARA - - UBX - 13000995 [19] u blox SARA - G3/SARA - U2 series System Integration Manual, document num. N2 series System Integration Manual, document number UBX - blox SARA - u [20] 17005143 - 16007243 u - blox Nested Design Application Note, document number UBX - [21] - ☞ For regular updates to u blox documentation and to receive product change notifications, register on our homepage ( ). blox.com - www.u Related documents 16029218 - R11 - UBX Page 114 of 116

115 SARA - System Integration Manual - R4/N4 series Revision history Name Date Revision Comments 2017 Jan 31 - - R01 sfal Initial release - 05 May 2017 sfal / sses R02 - Updated supported features and characteristics - Extended document applicability to SARA 01B product version - R410M - 24 - May R03 2017 sses Updated supported features and electrical characteristics sses 2017 - R04 19 - Jul Updated supported features and electrical characteristics 01B modules Added FCC and ISED info for SARA - R410M - - Extended document applicability to SARA R410M - 02B product version sses 2017 - R05 17 - Aug Updated supported features for “02” product version sses 2017 - Oct - 0 3 R06 Updated supported features for “02” product version 2018 - Jan sses 04 R07 - R410M - Updated SARA 02B product status - Updated USB, Power Saving and GPIO features description Improved Power - on sequence guidelines description Added I2C design guidelines description sses R08 26 - Feb - 2018 - Updated SARA R410M - 02B product status Extended document applicability to SARA R412M - 02B product version - Corrected power - on sequence description Corrected UART MUX description - Extended docu N410 - - R410M 52B and SARA ment applicability to SARA 02B - R09 10 - Aug - sses 2018 product version - Updated SARA R410M 02B product status - R412M - 02B and SARA - Updated features support plan for the product versions Clarified supported bands Updated UART TXD and CTS info Updated Approvals info and related remarks Added description of AT Inactivity Timer to enter power saving mode Minor other corrections 2018 R10 20 - - Sep lpah / sses Extended document applicability to SARA - R404M - 00B - 01 type number Clarified mode supported in frequency bands Added further guidelines for VCC and Antenna circuits design - - - 02B product status N410 - Updated SARA and SARA sses 9 201 - Feb R412M - R11 20 02B Revised supported bands certification info Updated Clarified VCC and RESET_N guidelines Minor other corrections and clarifications Revision history 16029218 - R11 - UBX Page 115 of 116

116 SARA - R4/N4 series - System Integration Manual Contact - blox.com . , visit us at www.u For complete contact information u - blox Offices Headquarters North, Central and South America Asia, Australia, Pacific Europe, Middle East, Africa u blox Singapore Pte. Ltd. - u - blox America, Inc. u - blox AG +1 703 483 3180 Phone: Phone: +65 6734 3811 [email protected] - blox.com [email protected] mail: - E - blox.com - mail: Phone: +41 44 722 74 44 E blox.com Support: - [email protected] blox.com - [email protected] mail: - E Regional Office West Coast: blox.com Support: suppo [email protected] - Regional Office Australia: Phone: +1 408 573 3640 blox.com - [email protected] mail: - E Phone: +61 2 8448 2016 - E mail: [email protected] - blox.com Technical Support: [email protected] Support: blox.com - +1 703 483 3185 Phone: Regional Office China (Beijing): - - blox.com [email protected] mail: E Phone: +86 10 68 133 545 - [email protected] mail: - E blox.com [email protected] - blox.com Support: Regional Office China (Chongqing): +86 23 6815 1588 Phone: E - mail: [email protected] - b lox.com blox.com - Support: [email protected] Regional Office China (Shanghai): +86 21 6090 4832 Phone: E - mail: [email protected] - blox.com Support: [email protected] - blox.com Regional Office China (Shenzhen): Phone: +86 755 8627 1083 [email protected] blox.com - E - mail: - Support: [email protected] blox.com dia: Regional Office In Phone: +91 80 405 092 00 - E mail: blox.com - [email protected] Su blox.com - [email protected] pport: Regional Office Japan (Osaka): 3660 +81 6 6941 Phone: E - mail: [email protected] blox.com - [email protected] Support: blox.com - Regional Office Japan (Tokyo): 3850 +81 3 5775 Phone: mail: - m blox.co E [email protected] - Support: [email protected] - blox.com Regional Office Korea: 0861 Phone: +82 2 542 E - mail: [email protected] - blox.com blox.com Support: support_kr @u - Regional Office Taiwan: +886 2 2657 1090 Phone: [email protected] blox.com E - - mail: Support: blox.com [email protected] - Contact 16029218 - R11 - UBX Page 116 of 116

Related documents

Michigan Merit Curriculum: Visual Arts, Music, Dance, and Theatre

Michigan Merit Curriculum: Visual Arts, Music, Dance, and Theatre

R I G O R • R E L E V A NC E • R E L AT I ONS H I P S • R I G O R • R E L E VA N C E • R E L AT I ONS H I P S • R I G O R • R E L E V A NC E • R E L A T I O N S H I P S • R I G O R • R E L E V A N C E...

More info »
An Introduction to Computer Networks

An Introduction to Computer Networks

An Introduction to Computer Networks Release 1.9.18 Peter L Dordal Mar 31, 2019

More info »
TRUMPF bending tools catalog EN

TRUMPF bending tools catalog EN

Tool- catalog Edition 2018 TRUMPF LASERdur Bending Tools TRUMPF Angle Measuring System ACB Machine Tools / Power Tools Laser Technology / Elektronics

More info »
Listing 7 Year Workplan Sept 2016

Listing 7 Year Workplan Sept 2016

National Listing Workplan 7-Year Workplan (September 2016 Version) : 12-month finding on a petition to list a species. If listing is warranted, we generally intend to proceed with a concurrent propose...

More info »
AN19   LT1070 Design Manual

AN19 LT1070 Design Manual

Application Note 19 June 1986 LT1070 Design Manual Carl Nelson INTRODUCTION Three terminal monolithic linear voltage regulators ap- Finally, there has been a notable lack of comprehensive peared almos...

More info »
City 2018 2019

City 2018 2019

2018–2019 CATALOG Fall 2018, Spring 2019, Summer 2019 1313 Park Blvd., San Diego, CA 92101 619-388-3400 www.sdcity.edu Ricky Shabazz, Ed.D. President San Diego City College is accredited by the Accred...

More info »
PassIssuanceList

PassIssuanceList

FEDERAL RECREATION AREAS WHERE INTERAGENCY PASSES ARE ISSUED This list is not comprehensive and may include errors; some Federal recreation sites are only open part-time or may change what passes are ...

More info »
PassIssuanceList

PassIssuanceList

FEDERAL RECREATION AREAS WHERE INTERAGENCY PASSES ARE ISSUED IMPORTANT! This list is not comprehensive and may include errors; some Federal recreation sites are only open part-time or may change what ...

More info »
u blox ZED F9P InterfaceDescription (UBX 18010854)

u blox ZED F9P InterfaceDescription (UBX 18010854)

u-blox ZED-F9P Interface Description Abstract The Interface Description describes the UBX (version 27. 10), NMEA and RTCM protocols and serves as a reference manual for the u-blox ZED-F9P high precisi...

More info »
PS Sec 15

PS Sec 15

State of California Civil Service Pay Scale - Alpha by Class Title Class Schem Full Class Title Code Pay CBID NT Prob. Mo. WWG MCR Period AR Crit Footnotes Compensation SISA ACCOUNT CLERK II 1733 CU70...

More info »
HIN202E, HIN206E, HIN207E, HIN208E, HIN211E, HIN213E, HIN232E Datasheet

HIN202E, HIN206E, HIN207E, HIN208E, HIN211E, HIN213E, HIN232E Datasheet

DATASHEET HIN202E, HIN206E, HIN207E, HIN 208E, HIN211E, HIN213E, HIN232E FN4315 ±15kV, ESD-Protected, +5V Powered, RS-232 Transmitters/Receiver s Rev 17.00 September 14, 2015 The HIN202E, HIN206E, HIN...

More info »
Instrument Rating   Airplane ACS (8B)

Instrument Rating Airplane ACS (8B)

FAA -S- ACS -8 B U.S. Department of Transportation Federal Aviation Administration Instrument Rating ‒ Airplane Airman Certification Standards June 2018 Flight Standards Service Washington, DC 20591

More info »
17 8652 GSR2018 FullReport web final

17 8652 GSR2018 FullReport web final

RENE WA BL E S 2018 GLOBAL STATUS REPORT A comprehensive annual overview of the state of renewable energy. 2018

More info »
v4 2 data quality document

v4 2 data quality document

Help Overview JPL D-33509 Rev. D Table Earth Observing System (EOS) BrO S T Aura Microwave Limb Sounder (MLS) CH S 3 Cl T CH Version 4.2x Level 2 data quality and S 3 CN T description document. CH S 3...

More info »
ELF Handling For Thread Local Storage

ELF Handling For Thread Local Storage

ELF Handling For Thread-Local Storage Ulrich Drepper, Red Hat Inc. [email protected] Version 0.20 December 21, 2005 Based on: Intel Itanium Processorspecific Application Binary Interface, May 2001, D...

More info »
Total Return Chart MonthlyReturns

Total Return Chart MonthlyReturns

Total Returns | April 30, 2019 Vanguard Total Return Chart Average Annual Total Returns* for Periods Ended April 30, 2019 Inception Fund Year Ticker Since Expense 10 Years No. Ratio Month Quarter Vang...

More info »
UAA Model Rules – January 2018

UAA Model Rules – January 2018

UNIFORM ACCOUNTANCY ACT MODEL RULES January 2018 Published by the National Association of State Boards of Accountancy 150 4th Avenue North, Nashville, TN 37219-2417

More info »
CPRI Specification V7.0

CPRI Specification V7.0

CPRI Specification V 7.0 (2015 -10- 09 ) Interface Specification Common Public Radio Interface (CPRI); Interface Specification The CPRI specification has been developed by Ericsson AB, Huawei Technolo...

More info »
PER 005 2

PER 005 2

PER 005 2 — Operations Personnel Training - - A. Introduction Title: Operations Personnel Training 1. Number: PER - 005 - 2 2. 3. Purpose : To ensure that personnel performing or supporting Real - tim...

More info »
DLDP Digital Language Survival Kit

DLDP Digital Language Survival Kit

L The D igital anguage roject P iversity D Digital Language Survival Kit The DLDP Recommendations to Improve Digital Vitality

More info »