Design of ion implanted MOSFET's with very small physical dimensions

Transcript

1 5> IEEE CIRCUITS, VOL. SC-9, NO. SOLID-ST.iTE OCTOBER 1974 JOURN.4L OF 2456 Source und Drain im Ersatzschaltbild eines Kapazitat auf ‘%ubnanosecond delays CMOS/ E. J. Boleky, using switching [31 Ent und Forxchungs- wicldwrgs- Siemenx MOS-Transistors,” in technology,” SOS silicon-gate 1971 Solid-State Int. Cir- 1, berichte 1972. X4-286, pp. 3$ no. Dig. cuit Conj., Tech. Papers, p. 225, R. Burns, “Switching J. of complementary+sym- [121 response Meyer, Boleliy J. E. E. J. and “High-performance low-power [41 circuits,” logic transistors MOS metry 25, vol. Rev., RCA memories CMOS using silicon-on-sapphire technology,” 1964. 627481, pp. Issue Micropower (Special on IEEE J. Solid-State Circuits Electronics), 1972. Apr. 135-145, pp. vol. SC-7, Gardner, and ‘[Introduction of Ahrons w. R. tech- [131 D. P. cir- symmetry complementary in performance and nology K. Bower, Dill, H. Aubuchon, G. W. and S. A. Thomp- G. R. [5’1 cuits,” Circuits Solid-State J. IEEE Tech- on Issue (Special ion effect gate by transistors field ‘[MOS son, im- masked jor SC-5, nology vol. Design), Integrated-Circuit 24–29, pp. plantation,” pp. ED-15, vol. Devices, Electron !t’’rams. IEEE 1970. Feb. 757-761, Oct. 1968. [141 “High F. Fang and H. Rupprecht, performance MOS in- F. with devices MOS ESFI “Complementary Tihanyi, J. gate [61 circuits ion using tegrated pre- technique,” implantation self adjustment by ion implantation,” in Proc. 5,th Iwt. Conj. at sented Germany, Munich, ESSDERC, 1973 the Microelectronics Munich, in Nov. 1972. Munchen- 27–29, pp. Wien, Germany: R. Oldenbourg Verlag, 437447. MOS E. J. Boleky, “The performance of complementary [71 substrates,” transistors on insulating RCA Rev., pp. 80, vol. 1970. 372-395, formation Goser, K. field gate insulated an in ‘[Channel [81 please p. see Michael Pomper, for a photograph and biography, Sienzen.s transistor ( IGFET) and its emrivalent circuit .“ effect no. 1, pp.’ 3-9, 1971. und Entwiclclungsbekhte, Forschungs- this issue. of 238 Brennan, A. E. Ruehli and P, metallization “Accurate A. [91 circuits for and packages,” capacitances integrated IEEE J. Solid-State Circwits Aug. (Corresp.), SC-8, vol. 289-290, pp. 1973. (Siemens SINAP Netzwerk Analyse Programm Paket), [101 Tlhanyi, p. see please biogra~hy, and photograph a for Jeno Siemens Germany. AG, Munich, 238 of this issue. ‘[Aufteilung der Gate-Kanal- Steinhubl, K. and Goser K, [111 of Design with Ion-Implanted MOSFET’S Physical Small Dimensions Very DENNARD, LIEMBER, IEEE, FRITZ H. GAENSSLEN, HWA-NIEN YU, MEMBER, IEEE, ROBERT LEO H. V. MEMBER) ERNEST BASSOUS, AND ANDRE IEEE, LEBLANC, MEMBER, IEEE RIDEOUT, R. paper considers the design, fabrication, and Absfracf—This SYMBOLS LIST OF switching devices suitable of MOSI?ET small very characterization semilogarithmic slope of sub- Inverse a dimensions 1 of for digital the of p. using circuits integrated order threshold characteristic. are presented which show how a conventional Scaling relationships reduced MOSFET device small improved An size. can be in struc- pro- Width of idealized step function D ion implantation to provide that shallow ture uses is presented chaDnel implant. for fde nonuniform pro- doping substrate a and regions drain and source Work difference between gate function AW, predict One-dimensional substrate the file. models to used are and substrate. threshold corresponding versus profile doping and the voltage and Dielectric constants for silicon transport A characteristic. voltage source current two-dimensional of short-channel model is relative used to predict degree the effects silicon dioxide. for device parameter combinations. Polysilicon-gate different current. Drain 0.5 ~ were fabricated, MOSFET’S with channel lengths as short as constant. Boltzmann’s pre- characteristics and the device measured and with compared constant. Unitless scaling dicted using from expected performance improvement values. The length. channel MOSFET small devices in highly miniaturized integrated circuits these very is projected. mobility. surface Effective concentration. carrier Intrinsic Substrate acceptor concentration. of Band bending in silicon at the onset received May Manuscript 20, 1974; 3, revised 1974. July substrate strong inversion for zero Watson IBM are aubhors The T. the with J. Center, Research Yorktown N.Y. 10598. Heights, voltage. Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

2 DENN.4m MOSFET’S ION-IMPLANTED : al. et 257 potential. *, junction Built-in GATE &*200A GATE tox=loooh ~ on Charge the electron. (1 :N+ ~N+o .___, ___, 1, oxide charge. Effective Q.,, -OILhp ‘+ ‘+ /l t Gate thickness. oxide ox /L\ --0 _- =. T Absolute temperature. 5P - L’l Vd, v., v,, Vaub and substrate volt- Drain, source, gate = 5 NA 10’5/cm3 x N~=25x10’6/cm ages. a a Vd. Drain voltage relative to source. (b) (a) V,-.”b relative to substrate. voltage Source v, principles Fig. 1. Illustration of device scaling with = K 5. (a) threshold voltage. Gate commercially Conventional (b) structure. device available w., Wd Source and drain depletion layer Scaled-down structure. device widths. w channel MOSFET width. channel relatively substrate, starting doped lightly this the reduces voltage threshold the of sensitivity implant INTRODUCTION in changes to bias. (“backdate”) source-to-substrate the EW HIGH resolution lithographic for techniques reduced This sensitivity” can “substrate then be traded forming integrated circuit patterns semiconductor N insulator of off 350-A thickness which for a thicker gate a offer linewidth of five to ten times decrease in and reproducibly fabricate to easier be to tends reliably. the optical contact masking approach which is com- over very Second, allows the formation of implantation ion Of in the semiconductor industry today. used monly the favor- drain regions which are more shallow source and has pattern beam electron techniques, new writing been main- while effects, short-channel respect with able to widely for experimental device used fabrication [1] – [4] combination resistance. sheet acceptable an taining The lithography projection optical and [5] X-ray while print- gives of a these features in an all-implanted design capability. ing have also exhibited high-resolution [6] realization Full the benefits of these new high-resolu- of switching device which can be fabricated thicker a with the tion lithographic techniques requires of development well-controlled gate if desired, which insulator has thresh- new designs, technologies, and structures which device old characteristics, and which has significantly reduced for can dimensions. very small optimized be interelectrode capacitances (e.g., drain-to-gate or drain- This the paper design, concerns fabrication, char- and to-substrate capacitances). very small MOSFET switching devices acterization of scaling This paper begins by describing principles the using dimensions circuits integrated digital for suitable conventional MOSFET to obtain a to applied are which p. reducing the source- that known is It 1 of order the of very structure capable of device improved a per- small (i.e., spacing to-drain channel FET an of length) the verification scaling formance. Experimental of the ap- changes undesirable to leads characteristics. device the in proach is then presented. Next, the fabrication process These the depletion changes significant become when for an scaled-down device structure using ion improved drain extend source the surrounding regions a over and this for considerations implantation Design described. is in under substrate silicon the region the of portion large on two are analytical tools: structure all-implanted based switching applications, the most For electrode. gate the a simple one-dimensional model that predicts the sub- in undesirable “short-channel” effect is a reduction the a long and for sensitivity strate devices, channel-length gate threshold which at which the device turns on, voltage that model current-transport two-dimensional predicts is aggravated by high drain voltages. It has been shown of turn-on device the chan- function a as characteristics that effects can be avoided by scaling these short-channel both length, The predicted results from are analyses nel vertical dimensions (e.g., gate insulator thickn- down the compared ;vith experimental data. Using the two-di- with the ) etc. depth, junction ess, horizontal along design mensional simulation, the sensitivity to of the while the decreasing proportionately also dimensions, Then, shown. is parameters Yarious attention detailed is design, intended for zero substrate givcll all to alternate applied doping substrate the increasing and voltages con- a scaling this Applying [8]. approach [7], to centration with bins, to respect advantages some offers thresh- which MOSFET conventional-size designed properly shows that a concludes paper the with Finally, control. old discus- a length channel the if required is insulator gate 200-A be expected to improvements performance the of sion be reduced 1 ~. is to to circuits integrated FET’s. small very these use from that paper major consideration of this A is to show how DEVICE SCALING the use of ion implantation leads an improved to design for small scaled-down MOSFET’S. First, the ability very a show [8] [7], scaling device of principles The in a low con- of ion implantation to accurately introduce concise be to trends design general the manner followed doping of doping atoms allows the substrate centration of the increasing and size the dccreming in performance lIOSFET state-of- a compares 1 Fig. devices. switching to be in- profile in the channel region under the gate creased a combined When manner. controlled a in with the-art n-channel lllOSFET [9] with a scaled-down Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

3 JOURFJ.iL OF SOLIC)-STATE CIRCUITS, OCTOBER 1974 IEEE 258 is substrates) the work function difference A~Vf p-type the device scaling principles to clevice clesignecl following cancels ~.’ of opposite sign, ancl approximately out *,J. be Fig. in shown structure larger The later. described i.e., band surface bencling the is in the poten- silicon ( the de- a~ailable commercially of typical reasonably is (a) 1 strong for zero substrate inversion of onset the at tial) tech- diffusion conventional using by vices fahricatecl (1) terms in appearing bias. It would *’ the that appear a insulator thickness 1OOO-A with gate a uses niques. It scaling rcxnain since and (2) they exact prevent approxi- substrate doping give to chosen bias substrate ancl a slightly the mately constant, actually increasing due to relative gate voltage I:r of approximately threshold 2 V *,’ ). eloping since ~0’ @ increased = (2kT/q) h] (.V.’/n, 10’5 5 potential. source the to doping of A X substrate However, the fixed substrate bias supply normally used cm-3 of sub- enough give an acceptable low to value is be with adjusted so that (~,,’ + n-channel devices can sensitivity substrate The impor- sensitivity. strate an is Thus, /K. + (~,, = ) V,,,,; V,,,,,) ap- by scaling clown the employing circuits switching digital in criterion tant voltages, plied substrate bias more other the applied than source followers because the design becomes difficult if drain or source the across drop potential the junctions, thethreshold voltage increases by more than a factor of or the the depletion region under gate, can be re- across range the source the of variation of voltage. full o~er two K. by CIUCeC{ illustrated Fig. 1 (a), the design pa- in clevice For the of All that clescribe the MOSFET clevice equations the about, L to 5 p. This rameters length channel the limit arises primarily from the penetration of the restriction above. demonstrated as scaled For be may characteristics by given [9] equation MOSFET the example, current surrounding area the into clrain the region depletion maxi- For electrode. the by a controlled normally gate V, vd/~ P,,,e.. w/K – – ~7t , _ ~ mum V ch-ain this pene- approximately of voltage 12-15 (Vet/K) = Id/K (3) — d tOx/K- L/ii — (–)( K ) potential surface tration the modify will significantly and the lower threshold voltage. factor K, is seen to be reduced by a, of set given any for smaller device new for suitable In order to clesigl~ a of in change no assuming voltages, applied mobility. a by scaled is device the L, of values in transformation is Actually, increased to clue slightly reduced mobility the and First, doping. three variables: dimension, voltage, substrate. impurity scattering in the heavier doped all linear clirnensions are reduced by a unitless scaling is It scaling generalize approach to the in- to possible &’K, t,ox’ = e.g., K, faCtOr primed where the parameters and current clensity. The field clude electric patterns refer reduction This device, scaled-down new the to distribution field electric in the scaled- maintained is il~cludes vertical dimensions such as insulator thick- gate a for except change in scale for the spatial device clown depth, ness, as well as the horizontal di- etc., junction coordinates. Furthermore, the electric field strength at volt- mensions of channel length and width. Second, the = V/c any because un?hanged is point corresponding are reduced by the factor ages applied to the device same V’/x’. the carrier velocity at Thus, point is also un- any Third, Vd,,/K). doping substrate concen- the (e.g., V~S’ = changed due to scaling and, hence, any saturation ve- tration is increased, agnin using the same scaling factor neglecting locity effects will be similar in both devices, shown = (i.e., ~Na). The clesign Na’ in Fig. 1 (b’) was microscopic lattice crystal fixed the to due erences cliff desired the to corresponds which 5 = K using obtained From reduced is current clevice the since (3), dimensions, p,. 1 reduction in channel length to per unit width channel IV K, the channel current of by observing The scaling relationships were developed by is by unchanged same the with consistent is This scaling, widths that the depletion layer in the scaled-down device area) sheet of carriers (i.e., density electrons per unit gate arc reducecl in proportion to the device climensions due to vicinity the clrain, of moving at the same velocity. In the ex- doping. the reducecl potentials ancl the increased For move lesser surface the from away the will carriers to a ample, the to due device, the in extent cliffusions. new shallower mobile Thus, will volume unit per carriers of clensity the (1) w,’ = + {[2cs,(V~’ }”2 V,-,,,JK)l/CIKN. m w,/Ic. the drain, higher in the space-charge region around bc turn-on at voltage decreased is The also [9] threshold complementing the higher density of immobile charge device so voltages reduced the to pro~ortion clirect in substrate, heavier the to clue rela- doped Other scaling that properly function will in clcvicc a circuit with the are given etc., time, delay density, power for tionships voltage This is shown by the threshold reducecl levels. discussed in a subsequent section in Table I ancl will be device. voltage equation for the scaled-down performance. circuit on sets of two scaling the verify to order In relationships, = (tO=/KCOf) { –Q,.,, + [~~,,~K~a(+s’ + Vs-s,,,/K)]’”} V,’ fabricated insulators experimental devices were with gate o + (AJVf + ~.’) = V,/K. (~) = 5). voltage The measured K drain of e., (i. A 200 ancl 1000 In the in Tt is primarily due reduction the de- (2) to = W/L 1, normalized devices, these of characteristics to in the while tOx/K, changes thickness, insulator creased 9. The ~ sets of characteristics are are shown in Fig. tin-o In most the voltage and doping terms tend to cancel out, quite similar when plotted with voltage and current scales of of cases type doping gates polysilicon (i.e., interest by of smaller clevice reduced the a factor of five, which substrate the of that to opposite on aluminum gates or confirms the scaling predictions. In Fig. 2, the exact Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

4 DENNARD at. ION-IMPbiNTED MOSFET’S et : 259 1,5~ VOLTAGE [V] GATE 20 100ox = tox 10 - *w=5p L v~ub=-?v sO.65V += - 0.5 5 Q 0 15 10 20 5 [V] DRAIN VOLTAGE (a) [v] VOLTAGE GATE 0.3 0.2 3 . IF + 0 ~ o 0 I 3 2 4 DRAIN VOLTAGE [v] (b) Fig. 2. Expcrimentzd drain voltage characteristics for (a) con- Fig. ventional, (b) scaled-down structures shown in and 1 nor- malized to W/L = 1. drain the and pinchoff cause to enough large is voltage 3.5 relationship, linear charact cristics exhibit the expected =10001! tox 3.0 When proj this axis voltage ccted the intcrccpt to gate =5V ‘ds voltage threshold a defines relationship linear for useful =-7V VSu~ 2.5 most logic circuit design purposes. =0,65V 1#, characteristics dcvicc the which in area Onc scale to fail fid 2,o inversion the is the of subthrcshold pr weak in region ’’2,,5 [#A] turn-on characteristic. [email protected] threshold, 1,, is exponentially scmilogarithrnic dependent on V, an inverse slopc, with 1.0 a, [10], [11] which for the scaled-down device is given by 0.5 flv,’ volts , ( 1,,’ () log,, dccadc a d = 1.6 1,2 .8 4 VOLTAGE GATE [V] Fig. Experimental turn-on characteristics for conventional 3. to and scaled-down devices shown in Fig. 1 normalized W/L The clcvice. as same the which is original larger the for 1. = dynamic memory circuits ~ is important lJaramctcr to because rcq~lired excursion voltage gate the determines it fortuitous the match current scale is thought to be on to state “off” Current low go froln high current the tile to uncertainty experimental some is there since magni- the in the attempt linear extend also to an In 11]. ( state ‘(on” channel tude of the length used to normalize the character- one operating the reduce could ~ to relationships scaling accurate istics (see Appendix). L1orc data from dcviccs cause lT70uld this but ~/K), = T’ (i.e., temperature in (4) on same larger the chip dimensions Icngth and with width mobility surface increase significant, <% effective the in pcrccnt ten mobility of shows an approximate reduction in the invalidate thereby and rclation- 12] [ scaling current the That doped heavier the with dcviccs for substrate. operation devices design to order at In (3). for shi~) of a by scales also voltage threshold of factor correctly temperature room the, accept must one above, and fact tllc cxpcrirncntal Fig. in verified 3, is five which SIIOJVS as desired. the subthreshold behavior does not scale’ that This nonscaling property of the subthreshold character- original for characteristics turn-on ~T. versus ~~ the istic is of particular concern to Ininiaturc dynamic menl- scaled-down the Shon-nj and the cases the For devices. Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

5 IEEE JOURNAL OF SOLID-STATE CIRCUITS, OCTOBER 1974 260 edges under gate electrode at the the of the source and t~* drain are then inhibited by the heavier doped surface a layer, pictured in Fig. 4(b), for the case of roughly turned-off device. The depletion regions under the source extend and doped lighter the into further much drain substrate. junctions these depletion regions With deeper (a) to tend in the lighter doped material which would merge control a loss of threshold would or, in the extreme, cause punchthrough at high drain voltages. However, the shal- lower junctions give a electric field pat- more favorable I \ substrate the when doping these avoids which tern effects concentration is properly chosen (i.e., is when it not too -Iv V,,,= 1 light), ion-im- capacitances The are reduced with the device layer planted structure due to the increased depletion separating and width drain source the from the substrate and [cf. 4(a) and 4(b) ], Figs. due to the natural self- ion alignment afforded by the process which implantation (b) reduces the overlap the the polysilicon gate over of The source and drain regions. thicker gate insulator also . . . but reduced gives gate capacitance, the performance -... p-Si -.. the by offset is respect gate in benefit this decreased field, 7.5x lo15cnl-3 1( . . . . . . . . . . . . . . . . . . . . “.-. . . . ) expected compensate for the To gate oxide and the thicker threshold drain for objective design a increase, maximum ,y~~=-lv 1 for V in the at design set ion-implanted 4 voltage was Fig. for sections cross Detailed struc- device scaled-down (a) 4. 3 4(b), to compared for the sc-sled-down device Fig. V and ture, device structure. ion-implanted corresponding (b) of Fig. 4(a). OF ION-IMPLANTED MOS~ET’s FABRICATION leakage circuits source-to-drain low require which ory The ion-implanted for the process MOS- fabrication currents. A four- will this in used now study be FET’s described. ION-IMPLANTED DESIGN DEVICE mask process was used to fabricate polysilicon-gate, n-channel MOSFET’s on a test chip which contains The to the lead presented just considerations scaling with p. lengths ranging from 0.5 to devices 10 channel shown length channel l-,P a with structure device in Fig. to pattern electron-beam use is aim eventual the Though improved corresponding the contrast, In’ (a). 4 design to exposure, it was more convenient use contact mask- the capability implantation afforded utilizing by ion is ing with high quality master masks for process develop- (b). 4 Fig. in shown device uses an ion-implanted The required high only is resolution purpose this For ment. doping initial substrate that is lower by about a factor pattern the for gate p 1.5 as small as lines uses which surface and of four, an implanted boron layer having a than concentration the greater somewhat con’eentration The which are reduced in the subsequent processing. cm 2 was resistivity substrate starting (i.e., about CI. Fig. of structure unimplanted the 4(a). throughout used cm-’). fabrication the of method for 1015 x thick The 7.5 and The concentration the depth of the implanted sur- described not is FET’s scent adj between isolation oxide chosen that are layer face this heavier doped region so to essential not is it as here, work be- and presented the will be completely within the surface depletion layer available. Follow- are techniques suitable several cause device on when grounded. with source turned is the the of low ing dry thermal growth the energy gate oxide, biased Thus, ground when potential, the source is above were ions B“ atoms/cmz) 101’ x (40 keV), low dose (6.7 into the depletion’ the lighter layer will extend deeper the implanted wafers, near into raising the boron doping “bulk” doped substrate, and the additional exposed All surface. the performed were implantations silicon small a will be reasonably charge and will cause only restrict diffusion growth gate of after order to in oxide in to required voltage gate-to-source modest increase the the regions. implanted substrate in turn on the device. With this improvement - poly After the channel implantation, a 3500-A thick can be the gate sensitivity insulator thickness increased was layer regions silicon gate the and n’, doped deposited, 350A gate maintain still and reasonable ‘as much as to a Next, 2000-A drain and source regions n“ delineated. shown be as voltage threshold later. will shal- to is philosophy design the of use aspect Another high deep formed by a high energy (100 keV), were dose x 10’5 atoms/cm’) As” implantation through the (4 n+ regions of depth comparable the to low implanted same 350-A oxide layer. During this step, however, the regions The layer. surface depletion p-type implanted Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

6 DENNARD ION-IMPLANTED al.: ei! MOSS13T’s 261 [v] V,(fo, vw~=-l) z:~ ,,-., 6 - ORIGINAL _ :\ IMPLANT l!i t5 i m- \, ! - ~ ‘E Ns ~ ; e -i +IOEALIZED ~ ~ STEP -/ X3 FUNCTION ; Z* : \ \ ‘1 / AFTER ;, 2 + ANNEALING # ; 4 0 ‘., ~ _ \l - I ‘... tdb 6. Calculated and experimental substrate sensitivity char- Fig. basic ion-implanted 5. Predicted substrate Fig. profile for doping acteristics for non-implanted devices with 200- gate 350-A and implanted through design 350-A the device ions BI1 keV 40 for ion-implanted insulators, for corresponding with and device gate insulator. gate insulator. 350-A channel the im- the from region masks gate polysilicon the boron is redistributed heavier as shown by the ing, absorbing The there. incident dose As” the of all plant, line. dashed were obtained using profiles predicted These etching process used to the gates results in a delineate program of computer a developed by F. F. Morehead penetration slight a allows which sidewall sloping of ASP5 laboratories. our The program assumes that boron atoms gate-to-drain ions the edges of underneath the gates, The in diffusing the silicon reflect the silicon-oxide inter- from 0.2 order the of of be to estimated is overlap source) (or face and thereby the surface concentration. For raise temperature p, steps that follow the The high processing modeling it is convenient to use a simple, ideal- purposes min implantations include 20 at 900°C, and 11 min at step-function the doping ized, of profile, representation 1000°C, which the out anneal to adequate than more is line ap- step ‘The Fig. in profile solid the by shown as 5. predicted profile rather well and proximates final the without out spreading greatly damage implantation the offers the few that it can be described by a advantage implanted resistances sheet O/D 50 were Typical doses. simple 5 Fig. in shown profiles three The parameters. the the for source and drain regions, and 40 fI/D for the have all dose. active same in- polysilicon areas. Following the AS’5 implant, a final for a profile, model thresh- step the Using determining layer oxide sulating deposited using was thick 2000-A old been developed from piecewise solutions has voltage Then, deposition. low-temperature chemical-vapor the condi- boundary appropriate equation Poisson’s of with regions were de- holes to the n+ and contact polysilicon delineated. applied was metalization the and fined, and only considers model one-dimensional The ], [11 tions implanted Electrical the shallow to directly contact account cannot and dimension vertical the for horizontal effects. the short-channel of shown in model are Results source regions was accomplished by a suitably drain and voltage threshold the plots source- which 6 versus Fig. to due junction avoid to metallurgy chosen penetration the final annealing After metaliza- alloying during step. to-substrate bias for the ion-implanted step profile shown Fig. comparison, For 5. substrate the shows also 6 Fig. in “C an in min 20 for forming 400 of step annealing tion device sensitivity the for nonimplanted characteristics density. fast-state the decrease to performed was gas background constant a and insulator gate 200-A a with ONE-DIMENSIONAL (LONG CHANNEL) ANALYSIS having a doping, device hypothetical and for 350-A a The substrate doping for profile the 40 keV, 6.7 X 10’1 the a con- and structure implanted like insulator gate atoms/cm~ gate 350-A implant incident on channel the nonimplanted the like doping background stant structure. oxide, Since the absorbs 3 per- oxide is shown in Fig. 5. The nonirnplanted 200-A case a low substrate exhibits of sensitivity, magnitude the but voltage threshold the silicon the of the incident dose, active dose in the cent is 6.5 x 10~1 atoms/cm2. The concentration at the time On the other hand, the nonimplanted 350-A also is low. given lightly implantation the of by the dashed Gaus- is with undesirably an but threshold, higher a shows case offers substrate high case The ion-implanted sensitivity. background doping level, iV~. sian function added to the range keV 40 standard and For projected the ions, B“ voltage a and threshold high sufficiently both a reason- deviation taken as 1300 A respectively and 500 i%, were > S,,I~ V~. sensitivity, for substrate low ably particularly 1 V. For the < 1 V, a steep slope occurs because Vs..,,,,, subsequent treatments heat the After 131. [ process- the of Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

7 IEEE JOURNAL OF SOLID-STATE CIRCUITS, OCTOBER 1974 262 ,~-5 layer the channel is obtained while inversion surface in CALCULATED,—— lop 1,2+ does in the depletion the silicon region under gate the L= 0,8/L ,+f ,+ ,+/ ~ 10-6 of the heavier ~, doped im- exceed step width not the 4V q Vd -m // // // v,u~ =-IV region. planted the inversion V, 1 > V,.,u,b For at H“ deple- +// +/’ +// 10-7 ~- ‘T- lighter substrate doped the tion region now extends into U /’r’f’ K K increases relatively then slowly voltage thethreshold and ~ 10-s i 4’ +1 a substrate fixed with Thus, of bias [11], with V..,,,,, I / ;1 g ~vfie~Qd~ ,8(3 ~ a K – range operating over the sensitivity substrate the V, 1 y{~,~l’ n 10-9 /-EXPERIMENTAL, voltage is V) 4 to of the source potential (e.g., ground L=9,75p J.17Y I h86p If ,~-lo low reasonably of non- slope the to similar very and the I ,0 1.2 .1.4 0.0 0,2 0.4 0.6 0.8 the threshold voltage implanted 200-A design. However, GATE , Vg (V) VOLTAGE is significantly higher for the design implanted which allows adequate margin so that, under worst case. design Fig. experimental subthreshold turn-on char- and Calucu!at.ed 7. for design for various channel ion-implanted acteristic basic reduce (e.g., the short-channel effects which conditions V,u, with lengths V, 1 – z V. z 4 V. will threshold high be still considerably), threshold the turned so enough that the device can be off to negligible a r 1 i i , 1 I 1 1 ap- as required for dynamic conduction level memory plications. Experimental results are also in Fig. 6 from given = L (i.e., devices long relatively on made measurements 10 ,p) have no short-channel effects. These data which agree A curve. calculated the with well reasonably x 10’1 atoms/cm2 implant was used to achieve 6 35 keV, slightly rather design value than higher result, the this x 1011 atoms/cm2. of 40 kel’ and 6,7 ANALYSIS CHANNEL) TWO-DIMENSIONAL (SHORT For devices sufficiently short-channel lengths, the with I_J???5 910 12345678 one-dimensional model is the for account to inadequate (MICRONS) L SPACING, SOURCE-DRAIN to penetration of threshold the lowering due voltage the region into normally controlled drain field channel and dependence of threshold Experimental 8. Fig. calculated ion-implanted basic for length channel on voltage with design by gate. While some models have been developed the V,.b v. 4 = v. v, –1 = this for problem behavior which account [14], the is the ion-implanted structure by the non- complicated for profile field electric an to leads which doping uniform pro- identified 3 as the actual current Fig. at the from difficult ion- the For approximate. to is that pattern jected the When V*. voltage, threshold computed char- current implanted case, the two-dimensional numerical in manner the acteristics gave they 3 plotted Fig. of were transport model of Kennedy and Mock [15], [16] was X 4 lengths. A at threshold for all device The band 10-8 The computer program was modified utilized. W. by bending, +,, at this threshold condition is approximately sub- the to [171 IIwang P. and Chang abrupt handle with other of Some V. 0.75 designs considered the device for considered profiles doping strate these devices. concentrations substrate heavier higher current at a gave The numerical current transport. model was used to used was A 10-7 of the simplicity, for so, threshold, value calculate behavior the turn-on of the ion-implanted de- small error in in cases with a resultant all Vt, computation of by a point-by-point the device cur- vice MOSFET’S meas- were lengths channel various with I“or voltage. gate of values Calculated increasing rent the of model. lu-ed to test the predictions two-dimensional values shown 7 for two Fig. of channel in results are determining experimentally for technique The the chan- well relatively long- as a for length as p., 1 of range the in the nel length for very short devices is described in Ap- device channel = L with 10 cases were normalized ,fl. All Fig. pendix. experimental results are plotted in 7 ‘Ike a to width-to-length ratio of unity, and a drain voltage and show good agreement with the curves, calculated length is of 4 V was used in all cases. As the channel the different L. of values somewhat considering especially 1 to rcdllccd the order of p, the turn-on characteristic in Another form of presentation of this data is shown a the shifts to of lowering a to due voltage gate lower a plotted is voltage threshold the where func- 8 as Fig. at occurs threshold voltage. The threshold voltage about tion voltage threshold The length. is channel of essen- a make characteristics turn-on transi- the where A 10-7 a by falls and L p, 2 > reasonably constant for tially tion linear from the exponential subthreshold behavior (a Vqz Id m semilogarithmic plot) response to the this on from then and L is decreased p, 2 to 1 amount as small be can level current This also behavior. square-law dccrca.ses more rapidly with further reductions in L, For Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

8 DENNARD [email protected] et al.: ION-IMPLANTED 263 CALCULATED THRESHOLD VOLTAGE vd=+4v “9 10-7 Ids FOR AMPERES [ VOLTS ) = y_?-.~ L=o.8p laop lo2p 10p BASIC N+ DESIGN (a) 7.5E15 ] Vm ~ ‘ v,”~ J ? DEEPER ~+ N+ SOURCE /ORAIN ---- JUNCTIONS characteristics drain voltage for ion- Experimental 9. Fig. basic (b) xj=o.4p V, with Vs.~ = —1 implanted design and L = 1.1 ~, 12.2 = W p, m load parameters; tracer Curve 4 voltage drain Q, .30 resistance P “ in V, voltage (U V apart. gate 8 steps each 0.5 V the set circuit of L could be nominal applications value somewhat than 1 ,P so that, over an expected greater reason- of deviation of L, the threshold voltage is range 1.3 ably well controlled. Forexample, L = * 0.3 pwould V~ Vfromchip O& l. = O.l give to this short- tochipdue be effect channel for would many tolerable This alone. circuit applications because of the tracking of different indeed control of degree this devices chip,if given a on character- ofL can be achieved. The experimental drain . for an ion-implanted MOSFET with a I.I-,P chan- istics Fig. source length are shown in nel 9 for the grounded is of condition. The general shape the characteristics the larger same as those observed ex- No devices. for much @vm :TRATE for traneous short-channel effects were observed drain Su voltages as 4 V. The experimental data in as Figs. large using Fig. 10. Threshold voltage calculated two-dimensional cur- using from taken were a devices channel im- 6-9 B“ transport model for various parameter conditions. A flat- rent X 10’1 and 35 and dose of keV energy 6.0 plantation of voltage band assumed, is V –1.1 respectively. atoms/cm2, used to test also were two-dimensional The simulations the considering that. boron dose implanted in the silicon of parameters. various to design the sensitivity the The is about expected was it case, this in less percent 20 that in Fig. 10 which tabulates values of given are results more short-channel effects would occur. However, the of channel length for the function a threshold voltage as identical com- show values calculated thresholds almost is 10(a) representa- idealized an indicated Fig. voltages. shallower With design. the pared to the basic implanta- design basic the for far. discussed been thus has that tion have and bias substrate zero use to possible is it still tion increase an was design basic the to perturbation first The heavier doped region substrate sensitivity since good the ,P. This was found to give an ap- in junction depth to 0.4 is depleted grounded a with turn-on at completely source. preciable reduction in threshold voltage for the shorter perturbation considers such a cascj again design The last devices in Fig. 10(b). Viewed another way, the minimum the long-chan- with a heavier same concentration to give increased by 20 percent be to have length device would calculations for (e) 10 this case [Fig. threshold 1. nel The 1.0 threshold to obtain a 1.2 comparable to (from to p) appreciably show the fact, In effect. short-channel less design. basic the shallower the of value the puts This p. case for threshold for is this 0.8 = L with device a perturbation Another perspective. in junctions the from L device the basic ,p. 1.0 = of an for as same the about was which design basic sub- a of use the was considered due apparently is important This design. improvement factor of 2, with a slightly strate doping lighter by a widths the source the around layer depletion reduced to higher concentration in the surface layer to give the the with and drain unc- j those across drop voltage lower same 1O(C) [Fig. device long-channel a for threshold ]. Also, tions. with these bias and doping conditions, the to be to similar proved devices smaller for results The the depletion layer depth in the silicon under the gate is the source where much less at threshold, particularly near from case of deeper j unc~ions. The next possible departure onlY band the this across depletion appears +$, bending, design shallower use the is of basic the implanta- boron a help may field of which the prevent region, penetration in tion wiih as half only deep, region, a channel the drain lines from the into this region where the device the to concentration heavier same give long-channel turn-on is controlled. the With ]. profile, 10(d) [Fig. threshold and shallower Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

9 JouRNAL soLm-STATE CIRCUITS, OCTOBER 1974 IEEE oF 264 1.2 I I i 1 [ I 1 I i *—* , 20 KeV,6Ellcm”2 2 0.4 - g 0,05 VOLTS (EXI?) + Vd = g - 0,2 =4 VOLTS (EXH Vd l I =4 (THEORY) Vd A VOLTS 1- I I I I I I 1 t 1 0.0 678910 01234 L?(p) Experimental and calculated dependence of threshold Fig. 11. channel length for ion-implanted zero substrate bias voltage on design. OF SUBSTRATE THE CHARACTERISTICS ZERO ‘“’r————————————l BIAS DESIGN the in Fig. 10(e) appears Since to design last shown terms of short-channel effects, it is in better be behaved its properties more fully. Experi- worthwhile to review corresponding to design were built mental devices this various lengths. In this case a with channel and tested x 10” atoms/cm2 Bll implant 20 used to keV, 6.0 was ~,o, o shallower implanted layer of approximately a obtain substrate Vsource - ) VOLTS ( for threshold these on Data [11]. depth 1OOO-A voltage is Fig. with 4 V applied to the drain presented in devices ion-implanted for characteristics sensitivity Substrate 12. Fig. to values. 11 calculated the and well very corresponds design with channel length as parameter. zero substrate bias for small also given in Data this figure, a drain voltage is channel of threshold variation less much showing with offers threshold control for strong in- design improved expected. The dependence of threshold voltage length, as version, flatter the by offset is advantage this subthresh- differ- on source-to-substrate bias is shown in Fig. 12 for characteristic. the applications such turn-on old For at held L, voltage drain-to-source The was ent values of is with the turn-on characteristic margin noise of Fig. 13 for this measurement. The a constant low results value if barely its bringing by off turned is device the suitable the indeed sensitivity the substrate is about that show ground. Furthermore, elevated temperature ag- to gate zero bias substrate the for same with design this for as situation the gravates memo~, dynamic for Thus, [18]. — the design with V.u~ = original 1 V. Note that smaller earlier presented V 1 – = [email protected] with design basic the is devices show a somewhat flatter substrate sensitivity preferred, thresholds with high at characteristic lower relatively of values source (and drain) voltage. SCALED-DOWN WITH PERFORMANCE DEVICES CIRCUIT The turn-on characteristics the for zero bias substrate The performance improvement expected from using design, both and calculated, are shown in experimental com- integrated MOSFET’S small very of in circuits small relatively The L. 13 for different values of I?ig. discussed parably section. this in small is dimensions shift is devices short-channel the for threshold in evident; alone First, the performance changes due to size reduction turn-on however, the rate is considerably slower for this given considerations scaling the from obtained are earlier. V,ub 1 = – V case shown in Fig. 7. This than for the case performance circuit the on influence The due to the the silicon depletion fact the to due is region in the that structural ion-implanted the of changes design is then for substrate bias shallow very is zero gate the under this discussed. voltage portion a that so case large gate given a of change perform- Table I lists the changes in integrated circuit the gate insulator capacitance rather dropped across is ance which follow from scaling the circuit dimensions, layer capacitance. This than across the silicon depletion voltages, and substrate doping in the same manner as the detail for these devices in another is discussed in some device changes described with respect to Fig. 1. These memory ap- paper [11 ]. The consequence for dynamic changes are indicated in terms of the dimensionless scal- though even that, is plications bias zero the substrate Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

10 DENNASD 10N-1MH,.4NTED iWOSFET’S at.: et 265 ,.-5 , , TABLE II II 20 6E KeV, cm-z LINES INTERCONNECTION FOR RESULTS SCALING . ]o-6 V,=4V / v$,~=o Parameter Factor Scaling . ,0-7 / R~ pL/Wt resistance, Line = W%~~ENTAL . + K voltage IR~/V drop Normalized K ,0-8 response Line time R~C 1 L=lOp . L=l.lp I/A density current Line K ~ & 10-9 . ,0-10 ~.li)o( *) ca- layer reduced widths. These depletion and reduced . A “ the by driven are pacitances resist- device unchanged a V/I decreased transition times with giving re- ances CTvj ,[ ; by circuit each of time delay the in reduction sultant a re- is circuit each of dissipation power The K. of factor 1.4 o 0.2 0.4 0.6 .0.8 1.0 1.2 by levels, current duced K’ due to the reduced voltage and vg [v] Since K8. the product power-delay improved by the so is device K2, by reduced also is circuit given or area of a char- Fig. 13. Calculated and experimental subthreshold turn-on the remains power density constant, Thus, even if many for design. bias substrate zero ion-implanted acteristics given more circuits are placed on a integrated circuit the cooling problem is essentially unchanged. chip, TABLE I indicated in Table arise a number of problems II, As SCALING RESULTS FOR CIRCUIT PERFORMANCE conductors that from the cross-sectional area of the fact length decreased by K2 while the only is K. is decreased by Parameter Device or Circuit Factor Scaling assumed thicknesses of the here conductors It is that the Device L, W’ dlmensiontO., 1/. with widths because are the necessarily along reduced Na Doping concentration K resolution requirements (e.g.j on of the more stringent Voltage V 1/. etching, remain considered The is etc. ). conductivity to Current 1 1/. Capacitance It EA l/K constant is to reasonable for which films down metal Delay time/circuit VC/Z 1/. dimensions free small mean the (until very becomes path VI dissipation/circnit Power 1 /K2 thickness), comparable to the and is also reasonable for density VI/A Power 1 semiconducting degenerately lines where doped solid volubility and impurity scattering considerations limit ing factor K. these results here in great detail Justifying any increase in conductivity. Under these assumptions a. is treatment simplified only so given. tedious, be would increases of resistance the directly with the given line a drop IR K. therefore in such a line is The voltages It is argued that all nodal are reduced in the factor scaling constant (with the decreased K levels) ~ but is current the reduced supply to in proportion miniaturized circuits times operating lower the to comparison in greater volt- voltages. This follows because the quiescent voltage levels The ages. unterminated of time transmission response an levels supply in digital MC)SFET circuits are either the limited line characteristically is constant time its by intermediate divider some or level given by a voltage R~C, this however, scaling; by which unchanged is makes consisting of or more devices, and because the resist- two higher switching difficult it of advantage take to the An V/I scaling. by unchanged is device of each ance the devices when signaI in inherent speeds scaled-down assumption is are elements made that parasitic resistance current over propagation lines is involved, Also, the long negligible either be will which scaling, by unchanged or K, conductor density in a scaled-down is increased by properly operate at examined subsequently. The circuits causes which conventional In concern, reliability a Vt lower voltages because the device threshold voltage conductivity these circuits, re- MOSFET are problems (2), and furthermore because the in shown scales as line- for significant become they but minor, latively be should reduced Vt proportionately tolerance spreads on dimensions. of widths be micron may problems The as the if each parameter in (2) is same well to controlled high in circumvented performance circuits widening by reduced, are margins Noise accuracy. percentage at but and use the power buses of by doped avoiding the n+ volt- coupling noise generated internally time same the lines propagation. signal for swings, are reduced by the lower signal voltage ages elements to the reduction in dimensions, all circuit Due of Use the ion-implanted this devices considered in to improvement performance similar give will that paper will devices) as well (i.e., interconnection lines as have I. K in given 5 = Table the with device scaled-down of by a This factor of K. reduced capacitances their occurs operating higher the with dcviccs implanted the For volt- by these area the in K’ of reduction the of because com- and higher threshold ages (4 V voltages of 3 V) instead by the partially is which ponents, decrease in cancelled instead V be will level (0.9 reduced of 0.4 V), the current films thinner to due K insulating the electrode spacing by Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

11 266 IEEE JOURNAL OF SOLID-STATE CIRCUrrS, OCTOBER 1974 of the to proportion in (Vg T’t) ‘/tox to about 80 percent — 12 I I 1 J current in the power The device. scaled-down dissipation - II cases. circuit per All device thus the is in about both same /: + factor the in less two of im- a about ate capacitances 10 - show and planted devices, will interconnection n+ lines 20 KeV, 6EII Cniz – 9 / + = Vt+ 0.5 VOLTS Vg same the to the lighter substrate due dop- improvement V,j = 0.05 VOLTS dec~:ased Some depth. junction ancl ing capacitance ele- 8 - v~ub=f) ~ such as lines metal would interconnection be ments – 47 the overall capacitance essentially that unchanged so z typical would be a somewhat less in improvement circuit x6 - /! + z a two. The delay circuit of than which per time factor z & 5 - is thus appears to be about the to proportional VC/I / + directly the for the and scaled-down implanted same for - 4 L= Lma~k-AL / micron Fig. in shown devices 4, 1 - 3 / NJMMARY 2 - / 0.86P AL= fabrication, considered design, the has paper This and / I - de- switching MOSFET small very of characterization /1 ,f/,!,!- 00 These highly to applicable vices. are considerations 4 2 3 I Lmosk (}) integrated circuits fabricated miniaturized by high-re- electron-beam as such lithographic solution techniques determine Fig. 14. Illustration to used technique experimental of set A of scaling relationships pattern consistent writing. channel length, L. a conventional device can were presented that show how scaling reduced in size; however, this be direct approach challenging some to leads technological requirements the on that observation gate shown as very thin such insulators. It was then how overcome an all ion-implanted structure can bc used to (Al) LP.m = WR.w area. per- these difficulties without sacrificing device or where channel 1s pCl,~~ and resistance, li,(.~~~ the sheet the formance. current transport two-dimensional A model > Vt — V~ value fixed of For channel. the of resistance a ion-implanted proved structures with use for modified 0, below-pinchoff the in on turned device with and the particularly valuable in predicting the relative degree of the region, channel sheet resistance is relatively inde- effects short-channel device pa- different arising from L~,,k versus w&han will Then, plot a L. of pendent of rameter the of objective general The combinations. study AL at axis Lm.,ll L~.~~ L, — AL because = t,he intercept MOSFET polysilicon-gate n-channel an design to was where dimen- AL the processing reduction in the mask is with a l-P channel length for high-density source-fol- sion this example An etching. and exposure to due of lower circuits such as those used in memories. dynamic technique in Fig. 14. illustrated is of combination satisfactory most The turn- subthreshold in Fig. used and W l?,,,. of values experimental The was on range, threshold control, and substrate sensitivity as sheet 14 were obtained resistance follows. First, the 35 achieved by an experimental lMOSFET a that used of the icm-implanted n+ region was determined using a 100 x 10” atoms/cm’ B“ channel implant, 6,0 a keV, structure. the Knowing relatively probe four-point large keV, a source/drain As” atoms/cm’ 10’5 x 4 implant, resistance sheet n+ and the source to us allows compute ~gate insulator, and an applied substrate bias of 350-A from W deduce to and R., and R. the resistance drain 1 design ion-implanted – in- V. Also presented was an n+ line. The resist- channel resistance of a long, slender, that tended for zero substrate bias is more attractive be from calculated can ance the suffers but control threshold of view of point from Finally an from range. turn-on subthreshold increased R. = VC,,J1, = (V, – R,,hnn + R1omi))/Id, + 2Rc + I,(R, sizable expected from the performance improvement (A2) of circuits integrated in MOSFET)S small very using projected. comparably small dimensions was drain, of resistance contact the is Rc the source or where load Rla,,l is the and cir- resistance of the measurement V + Vt VO = small a with 0.5 cuit. Id was determined at APPENDIX 50 of voltage or drain applied procedure The mV. 100 is DETERMINATION EXPERIMENTAL LENGTH GHANNEL OF one if accurate more MOSFET’S of set a and simple uses technique electrical effective the determining for A but same the having different values of L~.,~ all with for L from small MOSFET’S ex- very channel. length versus Rchan W,nnsl,. Then one needs only to plot of value in cwder to determine AL. L.,..], here. described is data perimental based is technique The Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

12 DENNARD ION-IMPL.4NTED MOSFET’S : U1. et 267 ACKNOWLEDGMENT in born was (M’65) Dennard H. Robert Tex., B.S. received the He 1932. in Terrell, acknowledge to valuable contributions of We wish the .S. electrical engineering in degrees M and Dall- University, Methodist ,Southern from who F. Crowder the L. B. ?vIorehead and F. provided as, and respectively, 1956, and 1954 in Tex., and design information. Also ion related implantations Institute Carnegie from degree Ph.D. the of l?. W. and Hwang of contributions the were important in 1958. Pa., Technology, Pittsburgh, Di- Research IBM the joined he 1958 In two-dimensional Chang J. J. computations. device to included experience his where vision study pre. mask the with assisted Walker and V. DiLonardo circuits and devices for new of and logic and devclo~ment memory of applications, and paration activities. The devices were fabri- testing advanced he Since 1963 techniques. communication datz has been the staff by the of cated silicon technology facility at the Heights, T. Watson IBM the at Center, Yorktown Research J. center. Research Watson J. T. he where Y., N. a integra- large-scale exploring group with worked models, (LSI), while making contributions in cost and yield tion memory MOSFET device and integrated circuit design, and FET RE~EREN-CES organizations. cells a of manager been has he 1971 Since and high group which is exploring density digital integrated circuits F. Tingj “Electron-beam H. C, fabri- and Hatzakis, M. Fung, [11 using advanced technology concepts such as electron beam ~at- ion of cation ” FET circuits, high-performance implanted exposure. tcrn Vat. Sci. Technol., J. 10, p. 1082, 1973. vol. [2] J. M. Pankrantz, H. T. Yuan, and L. T. Creagh, “A high- gain, low-noise transistor fabricated with electron beam lithography, Meeting, in Dig. Int. Electron Devices Tech. “ Dec. 1973, pp. 44-46. [31 H, N. Yu, R. H. Dennard, T. H. P. Chang, and M. Hatzakis, “.kn experimental high-density memory array fabricated in beam,” Papers, electron with 1973, Tech. Dig. IAWCC Feb, .i inn !w–wl . . Gaensslen was born in Tuebingen, Fritz H, [41 ‘ R. Voshchenkow, M, R. C. Henderson, A. F. W. Pease, P. 4, on Germany, 1931, He received October Wadsack, L. high speed p-channel ran- R. and Mallcry, ‘[A Dr. and Ing Dipl. the elec- in degrees Ing. electron access dom 1024-bit memory made litho- with trical Technical the from engineering Uni- Electron Devices Meeting, Dec. in Int. graphy,” Tech. Dig. 1973, pp. 138-140. in Germany, Munich, Munich, of versity 1966, 1959 and respectively. [51 L. D. I. Smith, “X-Ray lithography—a new ~pears and H. Prior Pro. Assistant as served he 1966 to Tech.nol., resolution replication process,” Solid State high of Electrical En- in fessor Department the 15, p. 21, 1972. vol. gineering, Munich, of University Technical Middlehoek, photoresist layers “Projection masking, thin S. [61 Germany. Munich, During this period he Develop., Res. J. IBM effects,” inn~fereuce p. ~:~ 14, vol. was the on synthesis of linear and working the u.~ Re. 1966 he joined Watson IB”M T. J. In ~i~ital networks. Yu, N. H. and Kuhn, L. Gaensslen, H, D&nard, ‘H. R. F, [71 a Center, Yorktown Heights, search where he is currently N,Y., the at presented devices,” switching MOS micron of “Design design process and device semiconductor group. of member a C., Devices Meeting, Washington, D. IEEE Int, Electron of interests advanced His current technical involve various aspects 1972. Dec. integrated circuits like miniaturization, device simulation, and [81 and A. N. Broers “Impact beam H. R. of electron Dennard, a. was he 1973 Scptcmbcr From implantation, on ion one year device Silicon Semicond, fabrication,” silicon on technology Germany, at the IBM Laboratory, Boeblingen, assignment Huff R. H. Publication), Bur- Sot. R. R. and (Electrochem. the member Dr. Gaensslcn is Gesell- Nachrichtentechnische of a gess, eds., pp. 830-841, 1973. Sclmft. L. Critchlow, R. H, Dennard, and S. E. Schuster, “Design D. [91 of field-effect tran. insulated-gate characteristics n-channel IBM sisters,” Res. Develop., vol. 17, p. 430, 1973. J. and R. M. Swanson comple- J. D. Meindl, “Ion-implanted [101 J. MOS transistors in low-voltage circuits,” IEEE mentary Solid-State Circuits, vol. SC-7, pp. 146-153, April 1972. ‘{Device A. LeBlanc, V. L. Rideout, F, H. Gaensslen, and [111 implanted design considerations for ion n-channel MOS- FET’s,” published. be to J. Develop., Res. IBM Shanghai, Hwa-Nien Yu (M’6,5) was born in [121 F. Fang A. B. Fowler, “Transport properties of elec- and F. He China, on January 17, 1929. received the trons inverted Rev. Ph~s. ” surfaces, Si in vol. 619, p. 169, Ph,D, degrees S., electrical B. M.S,, and in 1968, of University the from Illinois, engineering Johnson, W. S. IBM System Products Division, E. Fishkill, [131 1958, Urbana, in 1953, 1954, respectively. and N. private Y., communication. Re- a While he University, the at was threshold for analysis “An Lee, S. short voltage the of H, [141 Assistant search Computer Digital the in 16, channel IGFET’s,” Soiid-State Electron., p. vol. 1407, the of design the on worked and Laboratory 1973. IBM Illiac-11 the joining Since computer, P. mathemati- P. state Kennedy and D. C. Murley, “Steady [151 Laboratory been he in has 1957, Research cal ” field gate insulated the for theory effect transistor, exploratory various solid-state in engaged p. vol. 1, Res. 1973. 17, IBi14 Develop,, J. activities. research device Sys- Advanced the with working After of M. S. Mock, “A two-dimensional mathematical model [161 he Development Division from 1959 to the 1962, tems rejoined the Solid-State Elec- insulated-gate field-effect transistor,” speed Research in 1962 to work on the Division ger- ultra-high vol. tron., 1973. 601, p, 16, he 1967, Since menium technology. dcvicc in engaged been has IBM Division, Products System Hwang, P. and Chang W. [171 Essex Vt,, communication. Junction, private technology LSI research. He is currently silicon advanced device Semiconductor T. the at Technology IBM of Manager J. the [181 Troutman, R. R. for considerations design “Subthreshold Watson N.Y. Heights, Yorktown Center, Research insulated gate Solid-State J. IEEE ” transistors, field-effect Yu Dr. is a member of Sigma Xi. 1974. vol. SC-9, p. 55, April Circuits, Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

13 JOURNAL OF SOLID-STATE CIRCUITS, OCTOBER 1974 IEEE 268 infra where he worked for 1 year on 1959 born in Leo V. Rideout (S’61–M’65) was red the detectors at Centre National 1941. N.J. B.S.E.E. the received in He de- Issy-les- d’Etudes des Telecommunications, the from 1963 in honors with gree Univer- Moulineaux, he 1964 to 1960 From Seine. of sity M.S.E.E. Wisconsin, Madison, the A. Research Edison Thomas the at worked from in 1964 Stanford University, degree Laboratory Orange, in West where N.J., Ph.D. Stanford, in degree Calif., the and his included studies in arc dis- activities Univer- materials science in 1970 from the ultra violet absorption charge phenomena, sity of Southern California (U.S.C.), Los organic semiconductors, and spectroscopy, Angeles. under at His thesis work U.S.C. Research IBM the joined he Lab- In 1964 Crowell R. C. Prof. thermally concerned oratory, Heights, N.Y., to work Yorktown platinum assisted transport in sili- current semiconductors. on pres- is he staff Research the of member a As Schottky barriers, cide of study the in engaged ently in used processes and materials a he 1963 to 1965 was From member of the technical staff of circuits. of the silicon integrated fabrication Bell Telephone high-frequency on worked he where Laboratories Electrochemical Mr. Bassous is a member and Society of the transistors barriers Schottky metal-semiconductor and germanium the Science. of Advancement the for Association American as on he spent a year 1966 a Research In potassium tantalate. in department at the Tech- Assistant of Science the Materials of Eindhoven, Eindhoven, nological Netherlands, University The he 1970 In sulphide. cadmium in effects acoustoelectric studying device in the Research Esaki L. Dr. of IBM group research joined where he worked on fabrication and contact technology for multi- Andre (M’74) LeBlanc received the B.S. R. “superlattice” heterojunction structures using gallium-arsenide- engineering, and the in electrical degree and gallium-aluminum-arsenide. Since 1972 he has been phosphide degree from physics in M.S. the University design group a the semiconductor of device and circuit member of Vermont, Burlington, in 1956 and 1959, R. Dr. of Center, Research Watson J. T. IBM the at Dennard SC. respectively, and the D. degree in elec- N.Y, His research Heights, interests concern Yorktown present trical engineering from the University of silicon high density co-author or author the is He technology. FET Mexico, Albuquerque, 1962. in New technical 3 Patents. and 20 of papers U.S. Prior to joining IBM, Essex Junction, is of Dr. Rideout a Tau Society, Electrochemical the member G.E. with affiliated was he 1957, in Vt., as Phi Nu, Pi, Eta Kappa Beta Kappa Phi, and Sigma Xi. with Sandia an engineer and also electrical Cor~oration in conjunction with the Uni- in an educational took leave of 1959 versity of New Mexico. he 1, September on Egypt, Alexandria, in born was Bassous Ernest He of a presently is member doctorate. complete to absence his SC. degree in chemistry from the Uni- 1931. He received the B. IBM the Essex at Group Memory Exploratory the Laborato~, London, Londonj England in 1953, and the MS. versity of study interest a technical current his where Junction, of includes degree Institute Polytechnic the from chemistry of in physical publics. five authored has He devices. MOSFET short-channel N.Y. in 1965. Brooklyn, Brooklyn, well twelve and papers, as tions as several IBM Technical Re- the From at Physics and Chemistry taught he 1959 to 1954 ports. France Egypt. Alexandria, School, Boys’ British in to went He Sigma Dr. is a member of LeBlanc Xi and Tau Beta Pi. Authorized licensed use limited to: IEEE Xplore. Downloaded on January 23, 2009 at 21:27 from IEEE Xplore. Restrictions apply.

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