S 8264A/B/C Series  BATTERY PROTECTION IC

Transcript

1 S-8264A/B/C Series BATTERY PROTECTION IC FOR 2-SERIAL www.ablic.com TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) www.ablicinc.com © ABLIC Inc., 2005-2018 Rev.4.4 _00 lithium-ion rechargeable batteries, and incorporates a The S-8264A/B/C Series is used for secondary protection of high-accuracy voltage detection circuit and a delay circuit. Short-circuiting between cells makes it possible for serial connection of two cells to four cells. Features  High-accuracy voltage detection circuit for each cell (1) 1 to 4) = Overcharge detection voltage n (n • 25 mV ( + 25 ° C), Accuracy : ± 30 mV ( − 5 ° C to + 55 4.200 V to 4.800 V (in 50 mV steps) Accuracy : C) ± ° Overcharge hysteresis voltage n (n 1 to 4) • = − 0.520 0.210 V, − 0.390 ± 0.160 V, − − ± 0.110 V, ± 0.130 ± 0.06 V, None 0.260 Delay times for overcharge detection can be set by an in ternal circuit only (external capacitors are unnecessary) (2) (3) Output control function via CTL pin (CTL pin is pulled down internally) (S-8264A Series) n is pulled up internally) (S-8264C Series) Output control function via CTL pin (CTL pi (4) Output latch function after overcharge detection (S-8264B Series) Output form and logic CMOS output active “H” (5) Absolute maximum rating 26 V (6) High withstand voltage Wide operation voltage range 3.6 V to 24 V (7) − 40 ° C to + 85 ° (8) Wide operation temperature range C Low current consumption (9) 5.0 μ A max. ( • 25 ° C) At 3.5 V for each cell + At 2.3 V for each cell 4.0 μ A max. ( • 25 ° C) + *1 (10) Lead-free, Sn 100%, halogen-free  Product Name Structure ” for details. *1. Refer to “ Application  Lithium-ion rechargeable battery • packs (for secondary protection) Packages  • SNT-8A • 8-Pin TSSOP 1

2 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Block Diagrams (1) S-8264A Series VDD Overcharge SENSE detection comparator 1 + − Reference voltage 1 Overcharge VC1 detection Oscillator comparator 2 + vercharge O detection/release − delay circuit Reference voltage 2 Control logic Overcharge VC2 detection comparator 3 + − CO Reference voltage 3 Overcharge VC3 detection comparator 4 + − Reference voltage 4 VSS CTL Remark The diodes in the figure are parasitic diodes. Figure 1 2

3 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series (2) S-8264B Series VDD Overcharge SENSE detection comparator 1 + − Reference voltage 1 Overcharge VC1 detection Oscillator comparator 2 + O vercharge detection/release − delay circuit Reference voltage 2 Control Overcharge logic VC2 detection comparator 3 + − SR CO Reference voltage 3 latch Overcharge VC3 detection comparator 4 + − Reference voltage 4 VSS CTL UVLO Remark The diodes in the figure are parasitic diodes. Figure 2 3

4 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series S-8264C Series ) ( 3 VDD Overcharge SENSE detection comparator 1 + - Reference voltage 1 Overcharge VC1 detection Oscillator comparator 2 + vercharge O detection/release - delay circuit Reference voltage 2 Control Overcharge logic VC2 detection comparator 3 + - CO Reference voltage 3 Overcharge VC3 detection comparator 4 + - Reference voltage 4 VSS CTL Remark The diodes in the figure are parasitic diodes. Figure 3 4

5 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series Product Name Structure  1. Product Name (1) SNT-8A S -8264 x xx - I8T1 U Environmental code Lead-free (Sn 100%), halogen-free U: *1 Package abbreviation and IC packing specification I8T1: SNT-8A, Tape *2 Serial code Sequentially set from AA to AZ Product type A: Without CO pin output latch function (CTL pin is pulled down internally) B: With CO pin output latch function C: Without CO pin output latch function (CTL pin is pulled up internally) *1. Refer to the tape drawing. *2. Refer to “ 3. Product Name List ”. (2) 8-Pin TSSOP S -8264 x xx - T8T1 x Environmental code Lead-free (Sn 100%), halogen-free U: Lead-free (for details, please contact our sales office) G: *1 Package abbreviation and IC packing specification T8T1: 8-Pin TSSOP, Tape *2 Serial code Sequentially set from AA to AZ Product type A: Without CO pin output latch function (CTL pin is pulled down internally) B: With CO pin output latch function C: Without CO pin output latch function (CTL pin is pulled up internally) *1. Refer to the tape drawing. Refer to “ ”. *2. 3. Product Name List 2. Packages Drawing Code Package Name Package Tape Reel Land PH008-A-C- SNT-8A PH008-A-P-SD SD PH008-A-R-SD PH008-A-L-SD Environmental code = G FT008-A- P-SD FT008-E-C-SD FT008-E-R-SD 8-Pin TSSOP ⎯ FT008-E-R-S1 Environmental code = U FT008-A- P-SD FT008-E-C-SD 5

6 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series 3. Product Name List (1) S-8264A Series Table 1 SNT-8A Overcharge Detection Overcharge Hysteresis Overcharge Detection Product Name Output Form Voltage [V ] Delay Time [t Voltage [V ] ] CU HC CU − 0.390 ± 0.160 V ± ± 0.8 s CMOS output active “H” S-8264AAA-I8T1U 4.450 0.025 V 4.0 0.025 V − S-8264AAB-I8T1U 4.350 ± 0.160 V 4.0 ± 0.8 s CMOS output active “H” ± 0.390 ± 0.025 V − 0.390 ± 0.160 V 4.0 ± 0.8 s CMOS output active “H” 4.500 S-8264AAC-I8T1U 2.0 0.025 V 0.390 ± 0.160 V − ± 0.4 s CMOS output active “H” ± S-8264AAD-I8T1U 4.350 ± 0.025 V − 0.390 ± 0.160 V 4.0 ± 0.8 s CMOS output active “H” S-8264AAE-I8T1U 4.300 ± S-8264AAF-I8T1U 4.450 − 0.390 ± 0.160 V 2.0 ± 0.4 s CMOS output active “H” 0.025 V ± 0.025 V 0.390 ± 0.160 V 2.0 ± 0.4 s CMOS output active “H” S-8264AAG-I8T1U 4.300 − 4.0 ± 0.390 ± 0.160 V − ± 0.8 s CMOS output active “H” S-8264AAH-I8T1U 4.400 0.025 V ± 0.025 V − 0.390 ± 0.160 V 2.0 ± 0.4 s CMOS output active “H” S-8264AAI-I8T1U 4.400 S-8264AAJ-I8T1U 4.450 ± − 0.390 ± 0.160 V 5.65 ± 1.15 s CMOS output active “H” 0.025 V ± 0.160 V − 0.390 ± S-8264AAK-I8T1U 4.350 5.65 ± 1.15 s CMOS output active “H” 0.025 V 0.160 V S-8264AAO-I8T1U 4.400 − 0.390 ± 0.025 V 5.65 ± 1.15 s CMOS output active “H” ± 0.160 V CMOS output active “H” S-8264AAS-I8T1U 4.500 ± 0.025 V − 0.390 ± 1.15 s 5.65 ± S-8264AAT-I8T1U 4.550 0.025 V 0.390 ± 0.160 V 5.65 ± 1.15 s CMOS output active “H” ± − 0.390 ± 0.160 V − 0.025 V 5.65 ± 1.15 s CMOS output active “H” S-8264AAV-I8T1U 4.600 ± − 0.390 ± 0.160 V 0.025 V 2.0 ± 0.4 s CMOS output active “H” S-8264AAW-I8T1U 4.220 ± Table 2 8-Pin TSSOP Overcharge Detection Overcharge Hysteresis Overcharge Detection Product Name Output Form Voltage [V Voltage [V Delay Time [t ] ] ] HC CU CU ± 0.025 V − 0.390 ± 0.160 V 4.0 S-8264AAA-T8T1x 4.450 0.8 s CMOS output active “H” ± S-8264AAB-T8T1x 4.350 0.025 V − 0.390 ± ± 4.0 ± 0.8 s CMOS output active “H” 0.160 V 0.160 V − 0.390 ± ± 0.025 V S-8264AAK-T8T1U 4.350 5.65 ± 1.15 s CMOS output active “H” (2) S-8264B Series Table 3 SNT-8A Overcharge Detection Overcharge Detection Overcharge Hysteresis Output Form Product Name Voltage [V Voltage [V ] ] Delay Time [t ] CU HC CU ± 0.025 V − 0.390 S-8264BAA-I8T1U 4.450 0.160 V 4.0 ± 0.8 s CMOS output active “H” ± S-8264BAB-I8T1U 4.350 ± 0.025 V − 0.390 ± 0.160 V 4.0 ± 0.8 s CMOS output active “H” 0.8 s S-8264BAC-I8T1U 4.550 − 0.390 ± 0.160 V 4.0 ± 0.025 V CMOS output active “H” ± Table 4 8-Pin TSSOP Overcharge Detection Overcharge Detection Overcharge Hysteresis Output Form Product Name Voltage [V ] Voltage [V ] Delay Time [t ] CU HC CU CMOS output active “H” 0.8 s S-8264BAB-T8T1x 4.350 ± 0.025 V − 0.390 ± 0.160 V 4.0 ± 6

7 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series (3) S-8264C Series Table 5 SNT-8A Overcharge Detection Overcharge Hysteresis Overcharge Detection Product Name Output Form Voltage [V ] ] Voltage [V Delay Time [t ] CU HC CU 0.4 s 0.390 S-8264CAA-I8T1U 4.450 ± 0.025 V − CMOS output active “H” ± 0.160 V 2.0 ± 0.4 s CMOS output active “H” ± 0.025 V − 0.260 ± 0.110 V 2.0 ± S-8264CAB-I8T1U 4.220 Remark 1. Please contact our sales department for the products with detection volt age value other than those specified above. 2. x: G or U 3. Please select products of environmental code = U for Sn 100%, halogen-free products. 7

8 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Pin Configurations Table 6 Description Pin No. Symbol 1 Positive power input pin VDD 2 SENSE Positive voltage connection pin of battery 1 SNT-8A Negative voltage connection pin of battery 1 Top view 3 VC1 Positive voltage connection pin of battery 2 1 VDD 8 CO Negative voltage connection pin of battery 2 4 VC2 Positive voltage connection pin of battery 3 2 SENSE 7 CTL Negative voltage connection pin of battery 3 3 VSS VC1 6 5 VC3 Positive voltage connection pin of battery 4 4 5 VC2 VC3 Negative power input pin 6 VSS Negative voltage connection pin of battery 4 CO output control pin (S-8264A/C Series) 7 CTL Overcharge detection latch reset pin (S-8264B Series) 8 CO FET gate connection pin for charge control Figure 4 Table 7 Description Symbol Pin No. Positive power input pin VDD 1 SENSE Positive voltage connection pin of battery 1 2 8-Pin TSSOP Negative voltage connection pin of battery 1 Top view 3 VC1 Positive voltage connection pin of battery 2 CO VDD 8 1 Negative voltage connection pin of battery 2 4 VC2 SENSE CTL 2 7 Positive voltage connection pin of battery 3 VC1 VSS 3 6 Negative voltage connection pin of battery 3 VC2 VC3 4 5 VC3 5 Positive voltage connection pin of battery 4 Negative power input pin 6 VSS Negative voltage connection pin of battery 4 CO output control pin (S-8264A/C Series) 7 CTL Overcharge detection latch reset pin (S-8264B Series) 8 CO FET gate connection pin for charge control Figure 5 8

9 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series Absolute Maximum Ratings  Table 8 ° C unless otherwise specified) (Ta = 25 Item Applied Pin Rating Unit Symbol Input voltage between VDD and VSS VDD V V − 0.3 to V 26 + V SS SS DS Input pin voltage V 0.3 + SENSE, VC1, VC2, VC3, CTL V − 0.3 to V V DD IN SS V V CO V − 0.3 to V CO output pin voltage + 0.3 DD SS CO *1 450 SNT-8A mW P ⎯ Power dissipation D *1 700 mW 8-Pin TSSOP Operation ambient temperature T C ⎯ − 40 to + 85 ° opr 40 to T C ⎯ − Storage temperature + 125 ° stg *1. When mounted on board [Mounted board] t1.6 mm × (1) Board size : 114.3 mm × 76.2 mm (2) Name : JEDEC STANDARD51-7 The absolute maximum ratings are rated values exceeding which the product could suffer physical Caution damage. These values must therefore not be exceeded under any conditions. 800 8-Pin TSSOP ) [mW] 600 D SNT-8A 400 200 Power Dissipation (P 0 150 100 50 0 C] ° Ambient Temperature (Ta) [ Figure 6 Power Dissipation of Package (When Mounted on Board) 9

10 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Electrical Characteristics 1. Except Detection Delay Time Table 9 (Ta = ° C unless otherwise specified) 25 Test Test Item Symbol Condition Min. Typ. Max. Unit Circuit Condition DETECTION VOLTAGE 4.200 V to 4.800 V, adjustable, V 1 1 V V + 0.025 0.025 V − CUn CUn CUn Overcharge detection 25°C = Ta voltage n V CUn 4.200 V to 4.800 V, = 1, 2, 3, 4) (n adjustable, V 1 1 V V 0.030 + 0.030 − V CUn CUn CUn *1 + 55°C − = 5°C to Ta Overcharge hysteresis *2 V V 1 1 voltage n 0.520 − 0.210 ⎯ V + V 0.210 − HCn HCn HCn = 1, 2, 3, 4) (n INPUT VOLTAGE Operation voltage between ⎯ 3.6 V 24 V ⎯ ⎯ ⎯ DSOP VDD and VSS V CTL input “H” voltage V V 6 2 ×0.95 ⎯ ⎯ ⎯ CTLH DD V CTL input “L” voltage V ×0.4 V 6 2 ⎯ ⎯ ⎯ CTLL DD INPUT CURRENT Current consumption during ⎯ 3.5 V = V4 V1 = V2 = V3 = I 7 4 2.5 5.0 μ A OPE operation Current consumption during V1 ⎯ V2 = V3 = V4 = 2.3 V = 7 4 2.0 4.0 I A μ OPED overdischarge SENSE pin current I 8 5 1.5 3.2 = V2 = V3 = V4 = 3.5 V ⎯ V1 μ A SENSE VC1 pin current I 8 5 0 0.3 = V1 = V2 A V3 = V4 = 3.5 V − 0.3 μ VC1 VC2 pin current I 8 5 0 0.3 3.5 V = V3 = V1 = = − 0.3 V2 μ A V4 VC2 VC3 pin current I 8 5 0 0.3 V2 = V3 = V4 = = V1 − 0.3 μ A 3.5 V VC3 A/B Series 1.1 1.5 1.8 8 5 μ V4 A 3.5 V, = V2 = V3 = = V1 = V V DD CTL I CTL pin “H” current CTLH C Series 8 5 0.15 V4 = V3 = ⎯ = 3.5 V A μ = ⎯ V2 V1 = V V DD CTL A/B Series 8 5 V3 μ ⎯ A − = V2 = = V4 = 3.5 V, ⎯ 0.15 V1 V = 0 V CTL I CTL pin “L” current CTLL C Series 8 5 = V2 = V3 = V4 = 3.5 V A μ 10 − − 150 − 50 V1 V = 0 V CTL OUTPUT CURRENT CO pin sink current I mA 9 6 0.4 V = V +0.5 V ⎯ ⎯ COL SS COP CO pin source current I 9 6 20 V 0.5 V V A − ⎯ = ⎯ μ COH DD COP *1. Since products are not screened at high a nd low temperature, the specification fo r this temperature range is guaranteed by design, not tested in production. *2. 0.130 0.390 ± 0.160 V, − 0.260 ± 0.110 V, − − ± 0.060 V, or none, except for − 0.520 V hysteresis product circuits. The ) and the overcharge hysteresis voltage overcharge release voltage is the tota l of the overcharge detection voltage (V CUn (V ). HCn 10

11 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series 2. Detection Delay Time (1) S-8264AAA, S-8264AAB, S-8264AAC, S-8264AAE, S-8264AAH, S-8264BAA, S-8264BAB, S-8264BAC Table 10 C unless otherwise specified) = 25 (Ta ° Test Test Symbol Condition Min. Typ. Max. Unit Item Condition Circuit DELAY TIME t ⎯ 3.2 4.0 4.8 s 2 1 Overcharge detection delay time CU ⎯ 6 12 20 ms 3 1 t Overcharge timer reset delay time TR Overcharge release delay time ⎯ 51 64 77 ms 2 1 t CL ⎯ ⎯ ⎯ 2.5 ms 4 2 t CTL pin response time CTL 3.5 V, = V1 = V2 = V3 = V4 t 80 ms 5 3 Transition time to Test mode ⎯ ⎯ TST ≥ + 8.5 V V V E SENS DD (2) S-8264AAD, S-8264AAF, S-8264AAG, S-8264AAI, S-8264CAA, S-8264CAB Table 11 (Ta = 25 ° C unless otherwise specified) Test Test Symbol Condition Min. Typ. Max. Unit Item Condition Circuit DELAY TIME Overcharge detection delay time ⎯ 1.6 2.0 2.4 s 2 1 t CU t Overcharge timer reset delay time ⎯ 6 12 20 ms 3 1 TR Overcharge release delay time ⎯ 1.6 2.0 3.0 ms 2 1 t CL t ⎯ ⎯ CTL pin response time ⎯ 2.5 ms 4 2 CTL V1 = V2 = V3 = V4 = 3.5 V, t 80 ms 5 3 ⎯ Transition time to Test mode ⎯ TST V + 8.5 V ≥ V SENS E DD (3) S-8264AAJ, S-8264AAK, S-8264AAO, S-8264AAS, S-8264AAT, S-8264AAV Table 12 (Ta 25 ° C unless otherwise specified) = Test Test Item Symbol Condition Min. Typ. Max. Unit Condition Circuit DELAY TIME 6.8 s 2 1 Overcharge detection delay time t ⎯ 4.5 5.65 CU Overcharge timer reset delay time ⎯ 8 17 28 ms 3 1 t TR 70 88 110 ms 2 1 Overcharge release delay time t ⎯ CL 2.5 ms 4 t 2 ⎯ ⎯ ⎯ CTL pin response time CTL V1 = V2 = V3 = V4 = 3.5 V, ⎯ Transition time to Test mode 80 ms 5 3 ⎯ t TST ≥ V 8.5 V + V E SENS DD (4) S-8264AAW Table 13 25 C unless otherwise specified) = (Ta ° Test Test Symbol Condition Min. Typ. Max. Unit Item Condition Circuit DELAY TIME Overcharge detection delay time t ⎯ 1.6 2.0 2.4 s 2 1 CU t ⎯ 6 12 20 ms 3 1 Overcharge timer reset delay time TR ⎯ 51 64 77 ms 2 1 Overcharge release delay time t CL 2 t 2.5 ms 4 ⎯ CTL pin response time ⎯ ⎯ CTL 3.5 V, = = V4 = V3 V1 = V2 80 ms 5 3 t Transition time to Test mode ⎯ ⎯ TST ≥ V V + 8.5 V E SENS DD 11

12 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series Test Circuits  (1) Test Condition 1, Test Circuit 1 ) is the V1 voltage when CO is “H” after the Set V1, V2, V3, and V4 to 3.5 V. Overcharge detection voltage 1 (V CU1 voltage of V1 has been gradually increased. ) is the difference between V1 The overcharge hysteresis voltage (V HC1 and V when CO is “L” after the voltage of V1 has been gradually decreased. CU1 Overcharge detection voltage V (n = 2 to 4) and overcharge hysteresis V = (n 2 to 4) can be determined in the HCn CUn = 1. same way as when n (2) Test Condition 2, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 μ s) increase V1 up to 5.0 V. The overcharge detection delay time (t ) is the period from when V1 reached 5.0 V to wh en CO becomes “H”. After that, in a moment CU of time (within 10 s) decrease V1 down to 3.5 V. The overcharge release delay time (t μ ) is the period from when V1 CL has reached 3.5 V to when CO becomes “L”. (3) Test Condition 3, Test Circuit 1 μ s) increase V1 up to 5.0 V. This is defined as the Set V1, V2, V3, and V4 to 3.5 V and in a moment of time (within 10 first rise. Within t μ − a moment of time (within 10 s) decrease V1 down to 3.5 V and then 20 ms after the first rise, in CU s) restore up to 5.0 V. This is defined as the second rise. When the period from when in a moment of time (within 10 μ V1 was fallen to the second rise is short, CO becomes “H” after t has elapsed since the first rise. If the period from CU when V1 falls to the second rise is gradually made longer, CO becomes “H” when t has elapsed since the second rise. CU The overcharge timer reset delay time (t ) is the period from V1 fall till the second rise at that time. TR (4) Test Condition 4, Test Circuit 2 ) is the period In the S-8264A/C Series, set V1, V2, V3, and V4 to 3. 5 V and V5 to 14 V. The CTL pin response time (t CTL from when V5 reaches 0 V after V5 is in a moment of time (within 10 μ s) decreased down to 0 V to when CO becomes “H”. to 14 V after an overvolta ge is detected and CO becomes In the S-8264B Series, set V1, V2, V3, and V4 to 3.5 V and V5 “H”. In a moment of time (within 10 s) raise V5 from 0 V to 14 V. The CTL pin response time (t μ ) is the period from CTL when V5 becomes 14 V to when CO becomes “L”. (5) Test Condition 5, Test Circuit 3 After setting V1, V2, V3, and V4 to 3.5 V and V5 to 0 V, in a moment of time (within 10 μ s) increase V5 up to 8.5 V and decrease V5 again down to 0 V. When the period from wh en V5 was raised to when it has fallen is short, if an performed subsequently, the ov ercharge detection time is t overcharge detection operation is . However, when the CU period from when V5 is raised to when it is fallen is gr adually made longer, the overcharge detection time during the subsequent overcharge detection operation is shorter than t ) is the period from . The transition time to test mode (t CU TST when V5 was raised to when it has fallen at that time. 12

13 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series (6) Test Condition 6, Test Circuit 2 Set V1, V2, V3, and V4 to 3.5 V and V5 to 0 V. The CTL input “H” voltage (V ) is the maximum voltage of V5 when CTLH CO is “L” after V5 has been gradually increased. Next, set V5 to 14 V. The CTL input “L” voltage (V ) is the minimum CTLL voltage of V5 when CO is “H” after V5 has been gradually decreased. (7) Test Condition 7, Test Circuit 4 The current consumpti on during operation (I ) is the total of the currents that flow in the VDD pin and SENSE pin OPE when V1, V2, V3, and V4 are set to 3.5 V. The current consumpti on during overdischarge (I hat flow in the VDD pin and SENSE ) is the total of the currents t OPED pin when V1, V2, V3, and V4 are set to 2.3 V. (8) Test Condition 8, Test Circuit 5 The SENSE pin current (I ) is I3, the VC3 pin current ) is I1, the VC1 pin current (I ) is I2, the VC2 pin current (I VC1 VC2 SENSE (I ) is I4, and the CTL pin “H” current (I ) is I5 when V1, V2, V3, and V4 are set to 3.5 V, and V5 to 14 V. VC3 CTLH The CTL pin “L” current (I ) is I5 when V1, V2, V3, and V4 are set to 3.5 V and V5 to 0 V. CTLL (9) Test Condition 9, Test Circuit 6 Set SW1 to OFF and SW2 to ON. The CO pin sink current (I ) is I2 when V1, V2, V3, and V4 are set to 3.5 V and V6 COL to 0.5 V. Set SW1 and SW2 to OFF. Set V1 to V5, set V2, V3, and V4 to 3.0 V, and set V5 to 0.5 V. After t has elapsed, set CU SW1 to ON and SW2 to OFF. I1 is the CO pin source current (I ). COH 13

14 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series S-8264A/B/C Series S-8264A/B/C Series CO VDD VDD CO CTL SENSE SENSE CTL V V V1 V1 V5 VSS VC1 VSS VC1 V4 V4 V2 V2 VC3 VC2 VC2 VC3 V3 V3 Test Circuit 1 Test Circuit 2 S-8264A/B/C Series S-8264A/B/C Series CO VDD CO VDD A V5 CTL SENSE SENSE CTL V V1 V1 VSS VC1 VSS VC1 V4 V4 V2 V2 VC3 VC2 VC3 VC2 V3 V3 Test Circuit 3 Test Circuit 4 V5 I1 A SW1 S-8264A/B/C Series S-8264A/B/C Series VDD CO CO VDD I1 I5 SW2 A A SENSE CTL CTL SENSE I2 V1 V1 V5 V VC1 VSS VSS VC1 A I2 A V4 V4 V2 V2 I4 I3 VC2 VC3 VC3 VC2 A A V6 V3 V3 Test Circuit 6 Test Circuit 5 Figure 7 14

15 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series Operation  Remark “  Battery Protection IC Connection Example”. Refer to 1. Overcharge Detection ) during charging under normal When the voltage of one of the batteries ex ceeds the overcharge detection voltage (V CU conditions and the state is retained fo r the overcharge detection delay time (t ) or longer, CO becomes “H”. This state CU is called overcharge. Connecting FET to the CO pin provides charge control and a second protection. In the S-8264A/C Series, if the voltage of each of the batteries is lower than V + the overcharge hysteresis voltage CU ) and the state is retained for the overcharge release delay time (t ) or longer, CO becomes “L”. (V HC CL In the S-8264B Series, if the voltage of each of the batteries is lower than V or + V and the state is retained for t HC CU CL longer, the overcharge state is released; ho wever, CO stays at “H”. When the CT L pin is switched from “L” to “H”, CO becomes “L”. 2. Overcharge Timer Reset Operation When an overcharge release noise that forces the vo ltage of one of the batteri es temporarily below V is input during CU from when V is exceeded to when charging is stopped, t is continuously counted if the time the overcharge t CU CU CU release noise persists is shorter than the overcharge timer reset delay time (t ). Under the same conditions, if the time TR the overcharge release noise persists is t or longer, counting of t is reset once. After that, when V has been TR CU CU resumes. exceeded, counting t CU 15

16 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series 3. CTL Pin is used to control the output The S-8264A/B/C Series has a control pin. The CTL pin voltage of the CO pin. In the S-8264A/C Series, the CTL pin takes pr ecedence over the overcharge detection circuit. In the S-8264B Series, when the CTL pin is switched from “L” to “H”, a reset signal is output to the overcharge detection latch and CO becomes “L”. Table 14 Control via CTL Pin CO Pin CTL Pin S-8264C Series S-8264A Series S-8264B Series *1 *1 Normal state Normal state H ” “ Without latch * 1 *1 Normal state Open Normal state “ ” H * 1 Normal state H ” L “ “ “ H ” ” * 2 Latch reset − ”→“ L H ” − “ − ” “ H ”→“ L − − *1. The state is controlled by the overcharge detection circuit. *2. Latch reset becomes effective when the voltage of each of the batteries is lower than the overcharge detection ) ) has the overcharge hysteresis voltage (V ) and the overcharge release delay time (t + voltage (V HC CL CU elapsed. – – *1 *1 + + CTL CTL Pull-up resistor Pull-down resistor S-8264A/B Series S-8264C Series *1. The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage 2.8 V (Typ.), does not have the − hysteresis. Figure 8 Internal Equivalent Circuit of CTL Pin Caution 1. In the S-8264A/B Series, since the Ω to 12 M for Ω CTL pin implements high resistance of 8 M pull down, be careful of external noise application. If an external noise is applied, CO may become “H”. Perform thorough evaluation using the actual application. n or “L”, CO latches “H”. When the VDD pin 2. In the S-8264B Series, when the CTL pin is ope voltage is decreased to the UVLO voltage of 2 V (Typ.) or lower, the latch is reset. 16

17 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series 4. Test Mode In the S-8264A/B/C Series, the overcharge detection delay time (t ) can be shortened by entering the test mode. CU The test mode can be set by retaining the VDD pin voltage 8. 5 V or more higher than the SENSE pin voltage for at least C). The status is retained by the internal latch and the test mode is retained 80 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = 25 ° same voltage as that of the SENSE pin. even if the VDD pin voltage is decreased to the When CO becomes “H” when the delay time has elapsed afte r overcharge detection, the latch for retaining the test exits from the test mode. mode is reset and the S-8264A/B Series SENSE pin voltage VDD pin voltage 8.5 V or more Pin voltage V HCn V CUn Battery voltage (n = 1 to 4) Test mode = 80 ms max. t TST CO pin *1 t CL *1. = 4 s Typ. during normal mode, t = 64 ms Typ. In the product t CU CU In the product t = 2 s Typ. during normal mode, t = 32 ms Typ. CU CU In the product t = 88 ms Typ. = 5.65 s Typ. during normal mode, t CU CU Figure 9 Caution 1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the S-8264A/B/C Series returns to the normal mode. 2. Set the test mode when no batteries are overcharged. 3. The overcharge release delay time (t ) is not shortened in the test mode. CL 4. The overcharge timer reset delay time (t ) is not shortened in the test mode. TR 17

18 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Timing Charts 1. Overcharge Detection Operation (1) S-8264A/C Series V HCn V CUn Battery voltage (n = 1 to 4) CTL pin t or TR t or shorter TR longer CO pin t t CU CL t or shorter CU Figure 10 (2) S-8264B Series V HCn V CUn Battery voltage (n = 1 to 4) Reset operation disabled Reset operation enabled CTL pin t or TR t or shorter TR longer CO pin t t CL CU or shorter t CU Figure 11 18

19 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series 2. Overcharge Timer Reset Operation V HCn or t t or shorter TR TR t or TR longer shorter V CUn Battery voltage (n = 1 to 4) t CO pin TR or t CU t CU shorter Timer reset Figure 12 19

20 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series Battery Protection IC Connection Example  (1) 4-serial cell SCP + EB VDD R VDD C VDD SENSE R1 C1 BAT1 VC1 R2 S-8264A/B/C C2 BAT2 Series VC2 FET R3 C3 BAT3 VC3 CO D P R4 C4 BAT4 VSS CTL External R CTL *1 EB − input Figure 13 Table 14 * 1. Refer to for setting on external input. Table 15 Constants for External Components No. Part Min. Typ. Max. Unit R1 to R4 1 10 0.1 1 k Ω 2 0.01 0.1 1 C1 to C4, C μ F VDD 3 R 50 100 500 Ω VDD 4 R 0 100 500 Ω CTL Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R4 and to C1 to C4 and C . VDD 6 − 4. Set R so that the condition (R ≥ ) × (C1 to C4, C is satisfied. ) , C1 to C4, and C 5 × 10 VDD VDD VDD VDD 4 − 5. Set R1 to R4, C1 to C4, and C 10 × is ) ≥ 1 × (C1 to C4, C so that the condition (R1 to R4) VDD VDD satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the ent the three terminal protection fuse from cutoff. positive terminal of BAT1 last in order to prev 20

21 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series (2) 3-serial cell SCP EB + VDD R VDD C VDD SENSE R1 C1 BAT1 VC1 R2 S-8264A/B/C C2 BAT2 Series VC2 FET R3 C3 BAT3 VC3 CO D P VSS CTL External R CTL *1 EB − input Figure 14 1. * Table 14 for setting on external input. Refer to Table 16 Constants for External Components No. Part Min. Typ. Max. Unit 1 10 1 R1 to R3 0.1 k Ω 0.1 1 2 0.01 C1 to C3, C F μ VDD 50 100 500 3 R Ω VDD 4 R 0 100 500 Ω CTL Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C . VDD 6 − 4. Set R ) ) × (C1 to C3, C , C1 to C3, and C ≥ 5 × 10 is satisfied. so that the condition (R VDD VDD VDD VDD 4 − 5. Set R1 to R3, C1 to C3, and C 1 (C1 to C3, C × ) ≥ is so that the condition (R1 to R3) 10 × VDD VDD satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the rminal protection fuse from cutoff. positive terminal of BAT1 last in order to prevent the three te 21

22 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series (3) 2-serial cell SCP EB + VDD R VDD C VDD SENSE R1 C1 BAT1 VC1 R2 S-8264A/B/C C2 BAT2 Series VC2 FET VC3 CO D P VSS CTL External R *1 CTL EB − input Figure 15 1. Refer to * for setting on external input. Table 14 Table 17 Constants for External Components No. Part Min. Typ. Max. Unit 1 0.1 1 R1 and R2 10 k Ω 0.1 1 2 0.01 C1 and C2, C F μ VDD 50 100 500 3 R Ω VDD 4 R 0 100 500 Ω CTL Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and C . VDD 6 − 4. Set R ) ) × (C1 to C3, C , C1 to C3, and C ≥ 5 × 10 is satisfied. so that the condition (R VDD VDD VDD VDD 4 − 5. Set R1 to R3, C1 to C3, and C 1 (C1 to C3, C × ) ≥ is so that the condition (R1 to R3) 10 × VDD VDD satisfied. 6. Since “H” may be output at CO transiently when the battery is being connected, connect the rminal protection fuse from cutoff. positive terminal of BAT1 last in order to prevent the three te 22

23 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Precautions • Do not connect batteries charged with V or higher. If the connected batteries include a battery charged with + V CU HC V or higher, “H” may be output at CO after all pins are connected. + V HC CU • In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be tteries are connected. Perform thorough output of CO detection pulses when the ba restricted to prevent transient evaluation with the actual application circuit. In the S-8264B Series, “H” may be output at CO after all the pins are connected. In this case, set the CTL pin from “L” • to “H”. • Before the battery connection, short-circuit the battery side pins R and R1, shown in the figure in “  Battery VDD Protection IC Connection Example ”. The application conditions for the inpu t voltage, output voltage, and load current should not exceed the package power • dissipation. • Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit. g out of or in connection with any infringement of patents • ABLIC Inc. claims no responsibility for any disputes arisin owned by a third party by products including this IC. 23

24 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series  Example of Application Circuit 1. Overheat Protection via PTC (S-8264A Series) SCP + EB VDD R VDD C VDD SENSE R1 C1 BAT1 VC1 R2 S-8264A C2 BAT2 Series VC2 FET R3 C3 BAT3 VC3 CO D P R4 C4 BAT4 VSS C CTL CTL PTC EB − Figure 16 Cautions 1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in the S-8264A Series, connect the PT C before connecting batteries. 3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the S-8264A Series. 4. Since “H” may be output at CO transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three te rminal protection fuse from cutoff. [For SCP, contact] Global Sales & Marketing Division , Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan TEL + 81-3-5435-3946 Contact Us: http://ww w.dexerials.jp/en/ [For PTC, contact] Murata Manufacturing Co., Ltd. Thermistor Products Department Nagaokakyo-shi, Kyoto, 617-8555, Japan TEL +81-75-955-6863 Contact Us: http://www.murata.com/contact/index.html 24

25 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series  Characteristics (Typical Data) 1. Detection Voltage vs. Temperature Voltage vs. Temperature (1) Overcharge Detection (2) Overcharge Release Voltage vs. Temperature V = 4.3 V V = 0.52 V CU HC 4.40 3.90 4.35 3.85 [V] HC [V] 4.30 V 3.80 CU − V CU 4.25 3.75 V 4.20 3.70 0 75 75 0 25 50 25  85 25 50 25 85   40 40   C] Ta [  C] Ta [ 2. Current Consumption vs. Temperature Current Consumption during Normal Operation vs. Temperature (2) Current Consumption during Overdischarge vs. Temperature (1) V V = 14 V = 9.2 V DD DD 4.0 4.0 3.0 3.0 A] A] μ μ [ [ 2.0 2.0 OPED OPE I I 1.0 1.0 0.0 0.0 75 75 0 0 50 25 25 85 85  25 25 50    40 40   Ta [ C] C] Ta [ 3. Delay Time vs. Temperature (2) Overcharge Release Delay Time vs. Temperature (1) Overcharge Detection Delay Time vs. Temperature = 20 V V = 14 V V DD DD 90 6.0 80 5.0 70 [s] 4.0 60 [ms] CU t CL t 50 3.0 40 2.0 30 75 75 0 0 85 85 25  50 50 25 25  25 40   40 C]  Ta [ Ta [  C] 25

26 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series 4. Output Current vs. Temperature (2) CO Pin Source Current vs. V (1) CO Pin Sink Current vs. V DD DD Ta = 25 C Ta = 25 ° C ° 10.0 1000 7.5 700 A] μ [ 500 5.0 [mA] COH COL I I 2.5 250 0 0.0 10 10 15 25 20 15 20 25 5 5 0 0 [V] DD DD [V] V V 5. CTL Pin vs. Temperature (1) CTL Pin Threshold Voltage vs. Temperature (2) CTL Pin Input Resi stance vs. Temperature V = 14 V V = 14 V DD DD 14.0 12.0 ] 11.5 12.0  [V] [M 11.0 10.0 CTL TH.CTL R V 10.5 8.0 10.0 6.0 0 0 75 75  25 25 50 85 85 25 25  50   40 40 Ta [  C] Ta [  C] 26

27 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL-CELL PACK (SECONDARY PROTECTION) Rev.4.4 _00 S-8264A/B/C Series  Marking Specifications (1) SNT-8 A Top view (1) Blank 85 7 6 Product name vs. Product code (Refer to (2) to (4) Product code ) (4) (1) (2) (3) Blank (5), (6) Lot number (7) to (11) (7) (8) (5) (6) (9) 10 ) 11 ( ) ( 2 3 14 Product name vs. Product code (b) S-8264B Series (a) S-8264A Series Product Code Product Code Product Name Product Name (2) (3) (2) (4) (4) (3) S-8264BAA-I8T1U Q 6 A S-8264AAA-I8T1U Q 5 A S-8264BAB-I8T1U Q 6 B S-8264AAB-I8T1U Q 5 B S-8264BAC-I8T1U Q 6 C S-8264AAC-I8T1U Q 5 C S-8264AAD-I8T1U Q 5 D (c) S-8264C Series S-8264AAE-I8T1U Q 5 E Product Code Product Name S-8264AAF-I8T1U Q 5 F (2) (3) (4) S-8264AAG-I8T1U Q 5 G S-8264CAA-I8T1U Q 7 A S-8264AAH-I8T1U Q 5 H S-8264CAB-I8T1U Q 7 B S-8264AAI-I8T1U Q 5 I S-8264AAJ-I8T1U Q 5 J S-8264AAK-I8T1U Q 5 K S-8264AAO-I8T1U Q 5 O S-8264AAS-I8T1U Q 5 S S-8264AAT-I8T1U Q 5 T S-8264AAV-I8T1U Q 5 V S-8264AAW-I8T1U Q 5 W 27

28 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SE RIAL-CELL PACK (SECONDARY PROTECTION) _00 Rev.4.4 S-8264A/B/C Series (2) 8-Pin TSSOP Top view Product name: S8264 (Fixed) (1) to (5) Function code (6) to (8) 1 8 (1) (2) (3) (4) Lot number (9) to (14) 7 2 (7) (6) (5) (8) 6 3 14 ) (9) ( 10 ) ( 11 ) ( 12 ) ( 13 ) ( 4 5 Product name vs. Product code (a) S-8264A Series (b) S-8264B Series Product Code Product Code Product Name Product Name (3) (2) (1) (1) (3) (2) S-8264AAA-T8T1x A A A S-8264BAB-T8T1x B A B A B S-8264AAB-T8T1x A S-8264AAK-T8T1U A A K Remark 1. x: G or U 2. Please select products of environmental code = U for Sn 100%, halogen-free products. 28

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37 Disclaimers (Handling Precautions) (product data, specifications, figures, tables, programs, algorithms and application 1. All the information described herein circuit examples, etc.) is current as of publishing date of this docum ent and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not responsible for damages caused by the reasons other than th e products described herein ent of third-party intellectual property ri ght and any other right due to the use (hereinafter "the products") or infringem of the information described herein. 3. ABLIC Inc. is not responsible for damages ca used by the incorrect information described herein. ranges. Pay special attention to the absolute maximum ratings, 4. Be careful to use the products within their specified operation voltage range and electr ical characteristics, etc. ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the products outside their specified ranges. 5. When using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. n Exchange and Foreign Trade Act and all other export-related 6. When exporting the products, comply with the Foreig laws, and follow the required procedures. 7. The products must not be used or pr ovided (exported) for the purposes of the development of weapons of mass is not responsible for any provision (e xport) to those whose purpose is to destruction or military use. ABLIC Inc. develop, manufacture, use or store nuc lear, biological or chemical weapons, missiles, or other military use. 8. The products are not designed to be us ed as part of any device or equipmen t that may affect the human body, human life, or assets (such as medical equipment, disaster pr evention systems, security systems, combustion control s, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, systems, infrastructure control system aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do pments without prior written permission by ABLIC Inc. not apply the products to the above listed devices and equi Especially, the products cannot be us planted in the human body and devices ed for life support devices, devices im that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. therefore take responsibility to give thor ough consideration to safety design including The user of the products should redundancy, fire spread prevention measures, and ma injury or lfunction prevention to prevent accidents causing death , fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility. 10. The products are not designed to be radiation-proof. T he necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal us e. However, they contain chemical substances and heavy be put in the mouth. The fr acture surfaces of wafers and chips may be sharp. Be metals and should therefore not careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copy right information and know-how of ABLIC Inc. The information described herein does not convey any lic ense under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a thir d-party without the express permission of ABLIC Inc. is strictly prohibited. 14. For more details on the information de scribed herein, contact our sales office. 2.2-2018.06 www.ablic.com

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