AN408

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1 AN408 T PTIONS FOR A O -F REQUENCY , ERMINATION NY A -O UTPUT C LOCK G ENERATORS AND C LOCK B UFFERS NY 1. Introduction This application note provides termination recommendation s for connecting input and output clock signals to the Si533x and Si5356/55 family of timing ICs and is not applicable to any other Silic on Labs devices. The Si533x and Si5356/55 family of any-frequency, any-ou tput clock generators and cl ock buffers greatly simplifies the task of interfacing between many of today’s comm on signal types. Both the inputs and the outputs are compatible with single-end fferential signals (LVPECL, LVDS, HCSL, ed (LVTTL, CMOS, HSTL, SSTL) and/or di CML) and support multip le supply voltage levels (3.3 , 2.5, 1.8, or 1.5 V). All of the inputs and outputs are configured on a per-port basis offering unprecedented flexibility. Block di agrams of the devices are shown in 2 Figures 1 and 2. The Si5338 and Si5356 are I C-configured devices that lock to a crystal or external clock and generate up to four independent output frequencies. The Si5338 is compatible with both single-ended and differential clock formats, whereas the Si5356 is limited to single-ended clocks. The Si5334 is a pin-controlled 2 version of the Si5338 that does not have an I C interface. Similarly, the Si5355 is a pin-controlled version of the Si5356. The Si5330 is a non-PLL clock buffer device that pr ovides low jitter clock distribution and level translation. V DD Si5338/34 7, 24 Optional 20 XTAL VDDO0 Osc 22 CLK0A MultiSynth R0 ÷ 1 21 ÷M0 IN1 CLK0B 2 IN2 16 ÷ P1 VDDO1 3 18 IN3 CLK1A MultiSynth R1 ÷ 17 ÷M1 CLK1B PLL 4 15 IN4 VDDO2 14 P2 ÷ CLK2A MultiSynth 5 ÷ R2 IN5 13 ÷M2 CLK2B 6 IN6 11 VDDO3 12 2 10 SCL I C Control CLK3A MultiSynth 19 ÷ R3 SDA (Si5338 only) 9 ÷M3 CLK3B 8 INTR/ LOSLOL 23 GND V DD 7, 24 Si5330 20 VDDO0 22 CLK0A 21 CLK0B 16 VDDO1 18 CLK1A 1 IN1 17 CLK1B 2 IN2 15 VDDO2 3 IN3 14 CLK2A 13 CLK2B 11 8 VDDO3 LOS 10 CLK3A 9 CLK3B 4, 5, 6, 12, 19, 23 GND Figure 1. Si5338/34 and Si5330 Block Diagrams AN408 Copyright © 2013 by Silicon Laboratories Rev. 0.5 10/13

2 AN408 V DD Si5356 7, 24 20 XTAL VDDOA Osc 22 MultiSynth CLK0 R0 ÷ 1 21 ÷M0 CLK1 2 16 P1 ÷ VDDOB 4 18 CLKin CLK2 MultiSynth ÷ R1 17 ÷M1 CLK3 PLL 15 12 VDDOC SCL 19 14 CLK4 SDA MultiSynth R2 ÷ 3 13 ÷M2 I2C_LSB CLK5 2 6 C and Pin I OEB 5 Control 11 SSC_DIS VDDOD 8 10 INTR CLK6 MultiSynth ÷ R3 9 ÷M3 CLK7 23 GND V DD Si5355 7, 24 20 XTAL VDDOA Osc 22 MultiSynth CLK0 ÷ R0 1 21 ÷M0 CLK1 2 16 ÷ P1 VDDOB 4 18 CLKin CLK2 MultiSynth R1 ÷ 17 ÷M1 CLK3 PLL 15 3 VDDOC P1 12 14 CLK4 P2 MultiSynth ÷ R2 19 13 ÷M2 P3 CLK5 5 P4 Control 6 11 P5 VDDOD 8 10 LOS CLK6 MultiSynth R3 ÷ 9 ÷M3 CLK7 23 GND Figure 2. Si5356 and Si5355 Block Diagrams Rev. 0.5 2

3 AN408 2. Inputs 6/55 families support both sing s. The device supports up to The Si533x and Si535 le-ended and differential input two single-ended inputs (Pins 3 and 4) and two differ ential inputs (Pins 1,2, and 5,6). On the Si5338/34 and Si5356/55 devices, a crystal can be connected to Pins 1 and 2 instead of an input clock. Refer to “AN360: Crystal Selection Guide for Any-Frequency Devices” for more information on using the crystal input option. 2.1. Single-Ended Inputs The multi-format single-ended clock in puts of the Si533x and Si5356/55 are ac -coupled internally to remove any dc bias from the signal. This allows the de vice to trigger on a signal swing threshold instead of a specific voltage level (normally specified as V and V ). The receiver accepts any signal with a minimum voltage swing of 800 mV PP IL IH and a maximum of 3.73 V regardless of the core V supply. For best performance, the slew rate at input Pins 3 PP DD ts 3.3 V-tolerant even when the core voltage is powered and 4 must be greater than 1 V/ns. This makes the inpu with 1.8 V. An Si5338/34/56/55 should ha an 40/60%. An Si5330 should have an ve an input duty cycle no worse th input duty cycle no worse than 45/55%. 2.1.1. LVTTL/CMOS Inputs The only termination necessary when interfacing a CMOS dr iver to the Si533x and Si5356/55 is a source resistor (Rs) placed near the driver to help match its output im pedance to the transmission line impedance. In some cases, the value for this series resistor may be zero as it depends upon the CM OS driver characteristics. The CMOS  drivers in the Si533x and Si5356/55 are designed to work optimally into a 50 transmission line without an external source resistor. A typical CM OS signal connection is illu strated in Figure 3. Using this configuration, the receiver is capable of interfacing to 3.3, 2.5, or 1.8 V CMOS clock signals. V DD = 3.3 V, 2.5 V, 1.8 V Si533x/56/55 Rs 50 LVTTL/ CMOS Figure 3. Interfacing to an LVTTL/CMOS Input Signal 3 Rev. 0.5

4 AN408 2.1.2. Single-Ended SSTL and HSTL Inputs HSTL and SSTL single-ended clock inputs should be input to th e differential inputs, pins 1 and 2, of the Si533x with the circuit shown in Figure 4. resistor. If the SSTL/HSTL input is being driven by another Si533x device, Some drivers may require a series 25  the 25  series resistor is not required as this is integrated on-chip. The maximum recommended input frequency in this case is 350 MHz. Keep termination close to Si533x input pin of the V TT 50 0.1 uF Si533x 50 0.4 to 1.2 V pk-pk 1 Differential V DD Input 2 R 1 0.1 uF V TT R 2 0.1 uF SSTL_2, SSTL_18, HSTL R = 2.43 k 1 R = 2 k 2 SSTL_3 R = 2.43 k 1 = 2 k R 2 Figure 4. Single-Ended SSTL/HSTL Input to Pins 1 and 2 Rev. 0.5 4

5 AN408 gnal to a Differential Input 2.1.3. Applying a Single-Ended Si It is possible to interface any sing le-ended signal to the differential input pins (IN1/IN2 or IN5/IN6). The recommended interface for a signal that requires a 50  load is shown in Figure 5. On these inputs, it is important that the signal level be less than 1.2 V SE and greater than 0.4 V SE. The maximum recommended input PP PP frequency in this case is 350 MHz. Keep termination close to input pin of the Si533x 0.1 uF Si533x 50 0.4 to 1.2V pk-pk 50 0.1 uF Termination  Figure 5. Single-Ended Input Signal with 50 2.2. Differential Inputs The multi-format differential clock inputs of the Si533x will interface with today’s most common differential signals, such as LVDS, LVPECL, CML, and HCSL. The di fferential inputs are in must be ac-coupled ternally self-biased and th a voltage swing between 400 mV and . The receiver will accept a signal wi externally with a 0.1 μF capacitor 2.4 V at the input to the Si533x or else differential. Each half of the differential signal must not exceed 1.2 V PP PP the 1.3 V dc voltage limit may be exceeded. 2.2.1. LVDS Inputs When interfacing the Si533x device to an LVDS signal, a 100  termination is required at the input along with the required dc blocking capacitors as shown in Figure 6. Must be ac coupled Keep termination close to input pin of the Si533x 0.1 uF Si533x 50 100 50 LVDS 0.1 uF Figure 6. LVDS Input Signal 2.2.2. LVPECL Inputs ally self biased, an LVPECL signal may not be dc-coupled to Since the differential receiver of the Si533x is intern the device. Figure 7 shows so me common LVPECL connections that should not be used becaus e of the dc levels they present at the receiver’s input. 5 Rev. 0.5

6 AN408 V V DD DD V V DD DD DC Coupled with AC Coupled with Thevenin Termination R R 1 R 1 R 1 1 Thevenin Re-Biasing 50 50 50 50 LVPECL LVPECL R R 2 2 Rb R R Rb 2 2 Not Recommended May be Destructive to the Si533x Input Figure 7. Common LVPECL Connections that ing an LVPECL input signal to the Si 533x are shown in Figure 8. Typical Recommended configurations for interfac values for the bias resistors (Rb) range between 120  depending on the L VPECL driver. The 100  and 200  internally self-biased, no additional external bias is resistor provides line termination. Because the receiver is required. Another solution is to terminate the LVPECL driver wi on as shown in Figure 8b. th a Thevenin configurati  The values for R termination to V and R -2V. Given this, the recommended resistor are calculated to provide a 50  2 DD 1 values are R for V  =62.5 =2.5V. R  =127  = 250  and and R for V  =82.5 = 3.3 V, and R 2 DD 1 1 2 DD 6 Rev. 0.5

7 AN408 Keep termination close to input pin of the Si533x 3.3 V, 2.5 V 0.1 uF Si533x 50 100 50 LVPECL 0.1 uF Rb Rb Must be ac coupled Figure 8a—LVPECL Input Signal with Source Biasing Option Keep termination close to V V DD DD input pin of the Si533x Must be ac coupled R 1 R 1 V = 3.3 V, 2.5 V DD Si533x 0.1 uF 50 50 LVPECL 0.1 uF R R 2 2 = V – 2 V V DD T = 50 Ohm // R R 1 2 LVPECL Input Signal with Load Biasing Option Figure 8b— Figure 8. Recommended Options for Interfacing to an LVPECL Signal 7 Rev. 0.5

8 AN408 2.2.3. CML Inputs CML signals may be applied to the differential inputs of the Si533x. Since the Si533x differential inputs are sed, a CML signal may not be dc-coupled to the device. internally self-bia The recommended configurations for interfacing a CML in put signal to the Si533x are shown in Figure 9. The resistor provides line termination, and, since the receiv er is internally-biased, no additional external biasing  100 components are required. Keep termination close to Si533x input pin of the 0.1 uF Si533x 50 100 CML 50 0.1 uF Must be ac coupled Figure 9. CML Input Signal 2.2.4. Applying CMOS Level Signal to Differential Inputs Note that the maximum voltage level on the differential input pins on all Si533x must not exceed 1.3 V. To apply a CMOS signal to any of these pins, use the circuit shown in Figure 10. For a CMOS signal applied to these differential inputs, the maximum recommended frequency is 200 MHz. close to Keep R and R se sh the receiver 0.1 uF R Si533x se 50 CMOS Input Signal R sh 1.8 V CMOS 3.3 V CMOS  = 249 R R  = 499 se se  = 464 R  = 274 R sh sh 2.5 V CMOS 0.1 uF  R = 402 se = 357  R sh Figure 10. Applying a CMOS Level Signal to the Differential Inputs 8 Rev. 0.5

9 AN408 2.2.5. HCSL Inputs A typical HCSL driver has an open source output, which re quires an external series resistor and a resistor to  (Rs) and 50  (Rt). Note ground. The values of these resistors depend on the driver but are typically equal to 33 that the HCSL driver in the Si533x requires neither Rs nor Rt resistors. Other than two ac-coupling capacitors, no en interfacing an HCSL signal to the Si533x. additional external components are necessary wh Must be ac coupled 3.3V, 2.5V, 1.8V 0.1 uF Rs Si533x 50 Rs 50 HCSL 0.1 uF Rt Rt Figure 11. HCSL Input Signal to Si533x Rev. 0.5 9

10 AN408 3. Outputs erential or single-ended. The Si5356/55 devices only have The Si533x devices provide four outputs that can be diff generates two signals that can be configured as in- CMOS outputs. When configured as single-ended, the driver phase or complimentary. Each of the outputs has its own output supply pin, allowing the device to be used in mixed supply applications without the need for external level trans lators. Each output driver is configurable to support the following signal types: CMOS/LVTTL, SSTL, HSTL, LVPECL, LVDS, and HCSL. The Si5338 also supports a CML output driver. 3.1. CMOS/LVTTL Outputs The CMOS output driver has a controlled impedance of about 50  , which includes an internal series resistor of traces.  . For this reason, an external Rs series resistor is not recommended when driving 50  approximately 22  , a series resistor, Rs, should be used . A typical configur ation is shown in If the trace impedance is higher than 50 Figure 12. By default, the CMOS outputs of the driver are in-phase and can be used to drive two receivers. They can also be configured as complimentary outputs. The output supports 3.3, 2.5, and 1.8 V CMOS signal levels when the appropriate voltage is supplied to the extern al VDDO pin and the device is configured accordingly. 3.3, 2.5, or 1.8 V V DDOx LVTTL/ CMOS Si533x/56/55 CLKxA 50 CMOS CLKxB 50 Figure 12. Interfacing to a CMOS Receiver 3.1.1. 1.5 and 1.2 V CMOS Outputs The Si533x/55/56 output drivers natively support 3.3, 2.5, and 1.8 V CMOS. However, 1.5 and 1.2 V CMOS signals can be obtained using a two-resistor network as shown in Figure 13 and Table 1 below. Place R1 and R2 as close to the device output as possible. 1.8V or 2.5V, 3.3V, 1.8V or 3.3V, 2.5V, V DDOx V or 1.2 V 1.5 DDOx or 1.2 V 1.5 R 1 R 1 Si533x/56/55 Si533x/56/55 50 50 CLKxA CLKxA R 2 R 2 CMOS CMOS CLKxB CLKxB R 1 R 1 50 50 R 2 R 2 Figure 13. Interfacing to a 1.5 or 1.2 V CMOS Receiver Rev. 0.5 10

11 AN408 Table 1. Resistor Values for Interfacing to 1.5 and 1.2 V Receivers 1.5 V CMOS Output 1.2 V CMOS Output VDDOxR1R2R1R2  300  10  150  25 1.8 V  125   2.5 V 55  100 33  80  90 3.3 V 90   60 The resistor values in Table 1 were selected to maintain si gnal integrity, spec ifically rise/fall ti me, at the cost of current consumption is expe current consumption. The increase in cted to be on the order of 2 to 8 mA per output depending on VDDOx, 4 mA max with VDDOx of 1.8 V. 3.2. SSTL and HSTL Outputs The Si533x supports both SSTL and HSTL outputs, which can be single-ended or differential. The recommended supply can be generated using a simple voltage termination scheme for SSTL is shown in Figure 14. The V TT divider as shown below. SSTL (3.3, 2.5, or 1.8 V) V V TT TT HSTL (1.5 V) V DDOx SSTL_3 50   50 SSTL_2 Si533x SSTL_18 50 HSTL CLKxA SSTL or CLKxB HSTL 50 V DDO R 1 V TT SSTL_3 SSTL_2, SSTL_18, HSTL R 2 0.1 uF = 2.43k R R = 2k 1 1 = 2k R = 2k R 2 2 Figure 14. Interfacing the Si533x to an SSTL or HSTL Receiver 11 Rev. 0.5

12 AN408 3.3. LVPECL Outputs The LVPECL driver is configurable in both 3.3 V or 2.5 V standard LVPECL modes. The output driver can be ac- coupled or dc-coupled to the receiver. 3.3.1. DC-Coupled LVPECL Outputs The standard LVPECL driver su pports two commonly used dc-c oupled configurations. Bo th of these are shown in  to VDD–2 V, whic h is illustrated in Figure 15. LVPECL drivers were desig ned to be terminated with 50 can be supplied with a simple voltage divider as shown in Figure 15. Figure 15a. V TT quivalent to the An alternative method of terminating LVPECL is shown in Figure 15b, which is the Thevenin e load terminated to V –2.0 V. For 3.3 V LVPECL, use R =127  and  termination in Figure 15a. It provides a 50 DD 1  =62.5 =82.5  ; for 2.5 V LVPECL, use R and R =250  The only disadvantage to this type of termination R 1 2 2 supply. is that the Thevenin circuit consumes additional power from the V DDO Keep termination close to 3.3 V, 2.5 V the receiver V DDOx 50 3.3 V LVPECL Si533x 2.5 V LVPECL 50 CLKxA V LVPECL TT CLKxB 50 50 V – 2.0 V DDO – 2.0 V Figure 14a—DC Coupled Termination of 50 Ohms to V DD V V DDO DDO Keep termination close to 3.3 V, 2.5 V the receiver V R DDOx 1 R 1 3.3 V LVPECL Si533x 2.5 V LVPECL 50 CLKxA LVPECL CLKxB 50 3.3 V LVPECL = 127 Ohm R 1 V = V – 2.0 V DDO T R R 2 2 R = 82.5 Ohm 2 // R = 50 Ohm R 2 1 2.5 V LVPECL = 250 Ohm R 1 R = 62.5 Ohm 2 Figure 14b—DC Coupled with Thevenin Termination Figure 15. Interfacing the Si533x to an LVPECL Receiver Using DC Coupling 12 Rev. 0.5

13 AN408 3.3.2. AC Coupled LVPECL Outputs AC coupling is necessary when a receiver and a driver have compatible voltage swings but different common- mode voltages. AC coupling works well for dc-balanced signals, such as for 50% duty cycle clocks. Figure 16 describes two methods for ac coupling the standard LVPE CL driver. The Thevenin termination shown in Figure 16a (V – 1.3 V) supply is not available; however, it does is a convenient and common approach when a V DD BB supply can consume additional power. The termination method shown in Figure 16b consumes less power. A V BB be generated from a simple voltage divider circuit as shown in Figure 16. V V Keep termination close to DDO DDO 3.3 V, 2.5 V the receiver V DDOx R 1 R 1 3.3 V LVPECL 0.1 uF Si533x 2.5 V LVPECL 50 CLKxA LVPECL CLKxB 50 0.1 uF – 1.3 V V DDO 3.3 V LVPECL R R 2 2 Rb Rb R = 50 Ohm // R 1 2 R = 82.5 Ohm 1 R = 127 Ohm 2 2.5 V LVPECL Rb = 130 Ohm (2.5 V LVPECL) R = 62.5 Ohm 1 Rb = 200 Ohm (3.3 V LVPECL) = 250 Ohm R 2 Figure 15a—AC Coupled with Thevenin Termination Keep termination close to 3.3 V, 2.5 V the receiver 0.1 uF V DDOx 50 3.3 V LVPECL Si533x 2.5 V LVPECL 50 CLKxA V LVPECL BB CLKxB 0.1 uF 50 50 V – 1.3 V DDO Rb Rb Rb = 130 Ohm (2.5 V LVPECL) Rb = 200 Ohm (3.3 V LVPECL) Figure 15b—AC Coupled with 100 Ohm Termination VPECL Receiver Using AC Coupling Figure 16. Interfacing to an L Rev. 0.5 13

14 AN408 3.4. LVDS Outputs The LVDS output option provides a very simple and power-eff icient interface that requires no external biasing when connected to an LVDS receiver. An ac-coupled LVDS driver is often useful as a CML driver. The LVDS driver may be dc-coupled or ac-coupled to the re ceiver in 3.3 V or 2.5 V output mode. 3.4.1. AC-Coupled LVDS Outputs The Si5338/34 LVDS output can drive an ac-coupled load. The Si5330 LVDS output can only drive an ac-coupled load if the input to the Si5330 has a very well-controlled duty cycle like any S ilicon Labs PLL clock products. The ac  coupling capacitors may be placed at either the driver or re ceiver end, as long as they are placed prior to the 100  termination resistor as close to the receiver as possible, as shown in termination resistor. Keep the 100 Figure 17. When a 1.8 V output supply voltage is used, the LVDS output of the Si533x produces a common-mode d. In this case, it is be voltage of ~0.875 V, which does not support the LVDS standar st to ac-couple the output to the load. Keep termination close to the receiver 3.3 V or 2.5 V x V DDO Si533x 50 LVDS CLKxA LVDS 100 CLKxB 50 16a—DC-Coupled LVDS Output Keep termination close to the receiver 3.3V, 2.5V, or 1.8V x V DDO 0.1 uF Si533x 50 CLKxA LVDS 100 CLKxB 50 0.1 uF 16b—AC-Coupled LVDS Output Figure 17. Interfacing to an LVDS Receiver Rev. 0.5 14

15 AN408 3.5. HCSL Outputs Host clock signal level (HCSL) outputs are commonly used in PCI Express applications. A typical HCSL driver has an open source output that requires an external series resistor and a resist or to ground. The Si533x HCSL driver has integrated these resistors to simplify the interface to an HCSL receiver. No external components are necessary driver to an HCSL receiver. when connecting the Si533x HCSL 3.3, 2.5, or 1.8 V V DDOx Rs 50 HCSL CLKxA HCSL CLKxB Rs 50 Rt Rt Si533x Figure 18. Interfacing the Si533x to an HCSL Receiver 3.6. CML Outputs The Si5338 has a CML driver option. This driver can be used to replace an LVPECL driver in ac-coupled applications and save ~15 mA for each output driver in t he process. When using the CML driver, no external bias s to ground or Vtt should be connected. The CML driver is compliant with LVPECL resistors from the CML output peak-peak output levels; however, t tput voltage is not compliant to LVPECL specs. The CML he common-mode ou outputs. See Section 9 of “AN411: Configuring the Si5338 driver is individually available for all four differential ing the CML Driver option. The CML output driver option without ClockBuilder Desktop” for information on select should only be used when the output clock signal comes from an internal MultiSynth. long as the following conditions are met: The Si5338 CML output driver can be used as 1. Both pins of the differential output pair are ac coupled to the load. differential.  2. The load at the receiver is effectively 100 3. The Si5338 PLL is not bypassed. 4. The VDDOx supply for the CML driver voltage is 3.3 V or 2.5 V. tput voltage swing as the LVPECL driver. The CML driver has the same specified ou 1. Max Vsepp=.95V 2. Min Vsepp = .55 V 3. Typ Vsepp = .8 V Figure 19 shows the normal connection for the Si5338 CML Driver format. Figure 20 shows the expected termination for the Si5338 CML driver. This termination is most often within a CML receiver. Rev. 0.5 15

16 AN408 Si5338 CML Driver 50  Receiver + Do Not use external bias resistors  50 - Do Not use external bias resistors Figure 19. CML Driver Connection Si5338 CML Driver Effective Termination 50  +  50 Vbias 50   50 - Vbias can be any voltage with any source impedance Figure 20. Terminations for Si5338 CML Driver 16 Rev. 0.5

17 AN408 3.7. Interfacing the Si533x LV DS/LVPECL to a CML Receiver Current mode logic (CML) is transmitted differentially and terminated to 50  to Vcc as shown in Figure 21. A CML receiver can be driven with either an LVPECL or an LVDS outp ut depending on the sign al swing required by the receiver. A single-ended output swing from 550 mV to 960 mV is achieved when driving a CML receiver with an output swing, LVDS mode is recommen ded for producing a single-ended swing LVPECL output. For a reduced between 250 mV and 450 mV. Driving a CML Receiver Using the LVPECL Output 550 mV – 960 mV p-p Si533x CML 0.1 uF Receiver 50 50 Vcc 0.1 uF 50 LVPECL 50 Rb Rb Rb = 130 Ohms (2.5 V LVPECL) Rb = 200 Ohms (3.3 V LVPECL) Driving a CML Receiver Using the LVDS Output CML Receiver 250 mV - 450 mV p-p Si533x 0.1 uF 50 50 Vcc 0.1 uF 50 LVDS 50 Figure 21. Terminating an LVPECL or an LVDS Output to a CML Receiver 17 Rev. 0.5

18 AN408 OCUMENT C HANGE L IST D Revision 0.3 to 0.4  Updated Section 3.5. Revision 0.4 to 0.5  Updated Figure 10 on page 8.  Updated resistor values.  Updated "2.2.4. Applying CMOS Level Signal to Differential Inputs" on page 8. Added text to recomend max CMOS input frequency  into a differential input. Updated "2.1.2. Single-Ended SSTL and HSTL  Inputs" on page 4 and "2.1.3. Applying a Single- Ended Signal to a Differential Input" on page 5 to specify a max input frequency of 350 MHz.  Removed R1 and R2 and 0.1 μf cap from Figures 15 and 16.  Added maximum input frequency of 350 MHz to "2.1.2. Single-Ended SSTL and HSTL Inputs" on page 4 and "2.1.3. Applying a Single-Ended Signal to a Differential Input" on page 5.  Added "3.6. CML Outputs" on page 15.  Added "3.1.1. 1.5 and 1.2 V CMOS Outputs" on page 10. Rev. 0.5 18

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